Agilex 7 can HPS use HBM instead of DDR to connect to MPFE

[chander]

AGMF039 has 32GB of HBM. 16GB of HBM is on the same NoC as HPS. Is it possible for HPS to use this 16GB (or perhaps even 32GB) of HBM to be connected to its MPFE interface instead of DDR. 

Is there any example design for the same?

[aikeu]

Hi chander,

I dont see there is an example design for that.

Can search some of the example designs in the link below:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html

Thanks.

Regards,

Aik Eu

[chander]

Thanks for the link, it contains some wonderful design examples, but unfortunately not what we need. Btw is it architecturally possible to have the HPS boot of the HBM instead of DDR  via the MPFE? If so can someone guide us how we can possibly achieve this. 

[aikeu]

Hi chander,

There is no HBM reference guide for Agilex 7 HPS referring to Agilex 7 TRM.

https://www.intel.com/content/www/us/en/docs/programmable/683567/23-1/hard-processor-system-technical-reference.html

The available guide for building bootloader only uses DDR in the booting system.

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderAgilex7

Thanks.

Regards,

Aik Eu

[aikeu]

Hi chander,

I will close the thread if no further question.

Thanks.

Regards,

Aik Eu

[chander]

Thanks Aik Eu,

 Should we then conclude that its not technically feasible to have the HPS access HBM  via the MPFE? 

 Or should we  conclude that while its possible , there are no examples or documentation for it ?

regards

Chander

[JingyangTeh_Altera]

Hi

There are a few method of configuring the Agilex7 listed below:

• Configuration over JTAG
• Configuration from QSPI
• Configuration over AVST
• Configuration via Protocol
• Remote System Update (RSU)

https://www.intel.com/content/www/us/en/docs/programmable/683389/22-4/creating-the-configuration-files.html

The closes to your mentioned use case is to Configure over AVST. Where the Agilex7 is configured through the Avalon Stream by an Avalon Master.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Any update on this case?

Regards

Jingyang, Teh

[chander]

Hi,

  The query was regarding the HPS being able to access the HBM over the MPFE interface rather than the AXI interface. The HPS can only access a 4GB address space over the HPS-to-FPGA AXI interface, however via the MPFE it can access 16GB address space or more. The query was if HPS can access the HBM via MPFE.  

regards

Chander

[JingyangTeh_Altera · Accepted solution]

Hi

Apologize for the late reply.

The HBM could not be connected through the MPFE other than AXI.

Regards

Jingyang, Teh

[chander]

Thanks Jingyang Teh,

That helps answer the query.

regards

Chander

[JingyangTeh_Altera]

Hi

Do you have any follow up question for this case?

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh