Agilex5 JOP Bitstream Configuration Hang

[K606]

I am using this guide as a reference to try and add JOP capability to my project.

Following this step:

5. Connect the reset and clock to JOP component, also connect it's slave bus to the HPS LW bridge, and map it at offset 0x0002_0000

And instead set the offset to be 0x0300_0000.

Then sync Qsys, Generate HDL and compile the bitstream - all successfully, in HPS-First mode.

Note that on the identical design (with no JOP connected to lw-hps2fpga), the bitstream is configured without any problems. However with the JOP connected - in u-boot during the fpga load command, the bitstream configuration process exits with a time-out. 

Does anyone have some experience with this issue?

Many thanks,

K

[EstebanV_Altera]

@K606 can you share what you are seeing in after "fpga load... " command?

Could you please clarify if you are using Quartus 24.2?

[K606]

Hi Esteban,

Yes this is my log in u-boot:

In fact, I am using Quartus 24.3.

Many thanks,

K

[EstebanV_Altera]

Hi @K606 ,

This is my recommendation:

1. Once your SOF is generated after (Quartus Compilation).Re-generate the pair JIC/RBF. Using the u-boot-spl-dtb.hex file generated from the YOCTO build.

2. Flash your board with the new  <name>.hps.jic, and compile the Yocto build so the fresh <name>.core.rbf is added to the kernel.itb file in the SD card boot partition.

Often this failure happens because there is a mistmatch with the generated jic/rbf pair, so you have to be consistent and use the ones generated from:

     quartus_pfg \ -c <name>.sof ghrd_a5ed065bb32ae6sr0.jic \

     -o device=MT25QU128 \

     -o flash_loader=A5ED065BB32AE6SR0 \

    -o hps_path=u-boot-spl-dtb.hex \

    -o mode=ASX4 \

    -o hps=1

Please, give it a try and let me know.

~E.V.

[K606]

Hi @EstebanV_Altera,

Thanks for your fast reply!

Apologies, forgot to mention that I am booting via TFTP,  so do not need the SD card for anything except the section of the UBOOT script which fetches and boots the FPGA bitstream.

I have re-generated the .rbf in this way you suggest multiple times already, but each time I have this same hang!

Do you think it's possible to test the design on your end via TFTP?  In the meantime - I will flash the new JIC.

Many thanks,

K

[EstebanV_Altera]

@K606,

Are you programming the JIC file to the QSPI as well? or are you using Quartus programmer to flash the "<name>_hps_auto.sof".

In Agilex devices, you need two phases of the bitstream in "HPS First". phase 1 is the (jic of hps_auto.sof), phase 2 is the RBF. You need to update and use both.

Please confirm either you are flashing your QSPI with the JIC (this has to be done at least once) or you are using the "<name>_hps_auto.sof" to program your device (using the Quartus programmer) to kick-off the booting process.

See this

https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/e-series/premium/remote-debug/ug-remote-debug-agx5e-premium/#run-example

"Write the QSPI image $TOP_FOLDER/ghrd_a5ed065bb32ae6sr0.hps.jic to flash."

[K606]

Hi there @EstebanV_Altera,

So after compilation, I am doing the following to generate .hps.jic's:

quartus_pfg -c golden_top.sof golden_top_hps.sof -o hps_path=u-boot-spl-dtb.hex -o compression=on
quartus_pfg -c golden_top_hps.sof golden_top_hps.jic -o device=MT25QU512 -o flash_loader=A5ED065BB32AR0 -o mode=ASX4 -o hps=1

The names of the output binaries of this process are edited in the following.

No JOP IP integrated:
------------------------
Flash the QSPI on the board (in JTAG mode) with this command:

quartus_pgm -c 1 -m jtag -o "pvi;golden_top_hps_no_JOP_hps_first.hps.jic"

And then switch to AS mode, and boot the board over TFTP - here the board boots without issue through u-boot into the Linux userspace.

JOP IP integrated:
--------------------
Flash the QSPI on the board (in JTAG mode) with this command:

quartus_pgm -c 1 -m jtag -o "pvi;golden_top_hps_JOP_hps_first.hps.jic"

And then switch to AS mode, and boot the board over TFTP - here the hang occurred in u-boot once again with the error shared previously.

Note that the GHRD I am using requires Quartus-24.3, so I have been using this version.

I noticed that there is also this issue, maybe it is a source of the error? I don't think it should be, as it is for earlier versions of quartus.

[EstebanV_Altera]

Hi,

Yes, it seems like this is the same issue. I'm confirming internally if this was fixed in later Quartus versions.

~EstebanV

[K606]

Hi Esteban - thanks for checking here. If it is the case that this error has persisted, what do you recommend as a workaround?

Many Thanks,

K

[BoonBengT_Altera]

Hi @EstebanV_Altera,

Greetings, by any chances is there any updates form the internal alignment for the fixes on the latest quartus version?

Hope to hear from you soon.

Best Wishes

BB

[SueC_Altera]

Hi K606 and BoonBeng,

We have determined that the issue Esteban referred to is not related.

Please try programming the HPS first with a .sof that includes the JOP IP and check if that works. If not, please review the programmer error messages—there may be missing clocks during configuration.

If the .sof works, then it's worth checking which U-Boot version you are using. Recent branches print out debug error messages during configuration failures, which might help identify the problem.

Thanks,

Sue

[K606]

Hi Sue - could you share how you determined that this is not the issue?

Thanks,

K

[EstebanV_Altera · Accepted solution]

Hi @K606 

We internally evaluated your issue with the https://www.intel.com/content/www/us/en/support/programmable/articles/000098223.html and concluded they are not related (this is more related with the use of the JTAG chain, that does not prevents the HPS from booting). Your u-boot should be going through...

So, please, program your board using the .sof and this would give you and indication of why the "rbf" load is hanging.

Sorry for the delay in checking this out.

~E.V.

[K606]

I understand now - thanks @EstebanV_Altera 

[BoonBengT_Altera]

Hi @K606,

Greetings, as solution has been marked for your doubts, hence would assume challenge are overcome. 

Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes

BB