Any Cyclone V soc bare metal startup project settings available?

[CAlex]

Hi,

I successfully ran the sample on the rocketboards,

now I want to make my own project, 

do you guys have any setting guide for that?

Reguards.

[CAlex]

The main issue is from is order:

From the : intel-socfpga-hwlib\examples\CVAV\Altera-SoCFPGA-HardwareLib-Timer-CV-GNU\Makefile.inc

What's the default settings of the MAKE?

[aikeu]

Hi CAlex,

I will try to check if got any guide provided.

Anyway when I run baremetal application, I only consider the Makefile to add in those required files to support my application code other than the main.c.

Example like below:

EXAMPLE_SRC := main.c leds_cv.c pl330_tst.c alt_dma.c alt_dma_program.c alt_bridge_manager.c alt_fpga_manager.c alt_address_space.c

Thanks.

Regards,

Aik Eu

[CAlex]

Hi,

could you please provide 

python version and

this link resource (if that is not out of date)

in this link:Intel FPGA SoC FPGA Bare-Metal Developer Center Resources | Intel

Thank you

Reguards

Alex

[aikeu]

Hi CAlex,

I wasn't able to get any specific guide regarding the makefile.inc which you requested.

Are you not able to download the content from the link which you have provided? The link was able to work on my side.

May I know what is your issue when working with baremetal?

Thanks.

Regards,

Aik Eu

[CAlex]

Hi

Since you asked, all your examples provided are for ARM DS-5 Altera baremetal tool chains, and ARM DS uses linaro GCC tool chain.

During the project I met the questions like wrong tool chain settings, wrong libraries, wrong make file pointers, etc.

And for the python scripts to make the project, it is not workable with new python(3.10 or 3.9), so I basically cant use it.

There are three examples you provided for GNU, only the timer one make well. The other two can't make for errors.

So I now want to build my own project. But the instructions didn't work for me.

So could you please provide that resources directly to me please?

Reguards.

[CAlex]

Also, that's the make error for examples except timer one :

I'm using Linaro GNU 7.5.0 ,the same exact tool chain for your guide with the exact steps the guide says.

[aikeu]

Hi CAlex,

Did you perform git clone from https://github.com/altera-opensource/intel-socfpga-hwlib to install linaro?

git clone https://github.com/altera-opensource/intel-socfpga-hwlib 

cd intel-socfpga-hwlib/tools 

./install_linaro.sh 

Thanks.

Regards,

Aik Eu

[CAlex]

Yes I did. I downloaded and installed it as the User guide said, there is no skipping.

[CAlex]

Hi,

while I'm trying getting started preloader.ds launcher, there was an error:

The reset capability system is not available

Any idea to solve that?

[aikeu]

Hi CAlex,

Are you mentioned the part where you are trying to build the u-boot?

After you have obtained and built your ghrd, you will proceed to the next step to consider consider u-boot

Referring to this document on the part where you are going to build u-boot:

https://www.rocketboards.org/foswiki/Documentation/SoCEDS

Note that you will need the embedded_command_shell.sh to perform the build.

Thanks.

Regards,

Aik Eu

[CAlex]

Yes I build the u-boot , more accurate, the u-boot-spl from my GHRD.

Since I'm working on bare metal, I don't need u-boot.

As for preloader.ds part, it is from the GHRD itself.

The Linaro keep failing so I start to use ARMCC

Another wield issue occurred:

when mainully load the spl ,downloaded the axf file and start from the entry point,

it started at S:FFFF0000 where is the on chip RAM location.

But in the guide it should start at S:02000000 where the SDRAM at.

When I used the scatter pointed to 0x02000000, the program made an error from 0xFFFF0000.

So my question is how can I start from sdram?

Here is the reference PDF I followed:

BARE METAL USER GUIDE from your download center.

[aikeu]

Hi CAlex,

If you wanto run from ddr you will need the SPL(u-boot-splx4.sfp) to init the ddr first.

To boot from ddr you will need to run the below cmd when makding your application code:

Refer to the section(Software Examples) with the table https://github.com/altera-opensource/intel-socfpga-hwlib

if ddr the cmd will be:

make SEMIHOSTED=0 MEMORY=ddr

Thanks.

Regards,

Aik Eu

[CAlex]

Hi,

Yes I downloaded/ran the u-boot-spl and .bin file to _bss_end. And the console said it was succeed, 

After that I 

1. disconnect the preloader ds debug(connect only),i didn't find u-boot-splx4.sfp on my u-boot-socfpga/spl/ file, could you please tell me where to find it?

2. connect the program debug(start from entry point) with the scatter file cvav-ddr.scat (and built/link the interrupt_armcc.s) entrypoint is 0x0100_0000 with the Vector

I have the other debug started from 0x0200_0000 without Vector

3. Then the error showed up.

Reguards.

[CAlex]

Also I got several issues dealing with example makefile:

1. CP: option -n can't be used so I delete it

2. NEWLIB_ROOT is wrong , in my root system(X86_64 windows with MSYS 1.0) the root was:..\intel-socfpga-hwlib\tools\newlib\usr\arm-eabi 

instead of ..\intel-socfpga-hwlib\tools\newlib\usr\local\arm-eabi

I dont know weather  it's my failure to compeletely download it or it is because of the version/tool change.

3. The make file always point at ARM Compiler 5 (which did not exist in ARM DS), you may need to update the Makefile with armcc 6

And point three is my another new question (God bless us all) : how can I let the Makefile point to ARMCC 6?

The followed is the Makefile order:

/*--------------------------------------------------START FROM HERE-----------------------------------------------------------------*/

CROSS_COMPILE := arm-eabi-
CC := armcc
AS := armasm
LD := armlink
NM := $(CROSS_COMPILE)nm
OD := $(CROSS_COMPILE)objdump
OC := $(CROSS_COMPILE)objcopy

LINKER_SCRIPT := $(HWLIBS_SRC_ROOT)/src/linkerscripts/cvav-$(MEMORY).scat
MULTILIBFLAGS := --diag_error=warning --diag_suppress=9931 --cpu=Cortex-A9 --no_unaligned_access
CFLAGS := -g -O0 --c99 --strict $(MULTILIBFLAGS) $(INCLUDE_DIRS) -D$(ALT_DEVICE_FAMILY) -DALT_FPGA_ENABLE_DMA_SUPPORT=1 -D_USE_STDLIB -DALT_BRIDGE_PROVISION_F2S_SUPPORT -D$(ALT_DEVICE) $(UART_DEFINES) $(ADD_CFLAGS_ARMCC)
ASMFLAGS := -g $(MULTILIBFLAGS)
LDFLAGS := --strict $(MULTILIBFLAGS) --entry=alt_interrupt_vector --scatter=$(LINKER_SCRIPT)
ifeq ($(SEMIHOSTED), 1)
LDFLAGS += --keep=__auto_semihosting
endif
ODFLAGS := -d
OCFLAGS := --bin --output=

/*-------------------------------------------------------END------------------------------------------------------------------------------------*/

The following is the error when trying to compile the first file:

process_begin: CreateProcess(NULL, armcc -g -O0 --c99 --strict --diag_error=warning --diag_suppress=9931 --cpu=Cortex-A9 --no_unaligned_access -Ilib -Ihwlib/include -Ihwlib/include/soc_cv_av -Ihwlib/include/soc_cv_av/socal -ID:\board\cyclone_V_soc\intel-socfpga-hwlib\tools\newlib\usr\arm-eabi/include -Dsoc_cv_av -DALT_FPGA_ENABLE_DMA_SUPPORT=1 -D_USE_STDLIB -DALT_BRIDGE_PROVISION_F2S_SUPPORT -DCYCLONEV -DPRINTF_HOST -c hwlib/src/hwmgr/alt_address_space.c -o objs_ARMCC_CYCLONEV/alt_address_space.o, ...) failed.

Reguards.

[aikeu]

Hi CAlex,

I build everything in linux environment without using Arm DS

I was using the building bootloader to build and get the spl from https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Boot_from_QSPI

"cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/spl/u-boot-splx4.sfp \"

After install the toolchain, I will export the path as below to further build the application.

######################################## 

# get hwlibs, install toolchain 

######################################## 

git clone https://github.com/altera-opensource/intel-socfpga-hwlib 

cd intel-socfpga-hwlib/tools 

./install_linaro.sh 

export PATH=`pwd`/gcc/bin:$PATH

Thanks.

Regards,

Aik Eu

[CAlex]

Hi,

I'm doing the baremetal project.

can you explain what is this file do?

Another question is that when using spl to debug the board, what's the MSEL setting? Does it matter?

For once I successfully download the spl and initialize the DDR. 

But now I can't with several wield errors.

Reguards.

[CAlex]

Hi

while debug the preloader:

WARNING(CMD399-COR168):
# in D:\board\cyclone_V_soc\GHRD\software\software\bootloader\debug-spl.ds:8 while executing: start
! Failed to start the target
! No function named "main" could be found
WARNING(CMD407): Trying the entry point instead
Execution stopped in SVC mode at S:0xFFFF0000
In boot0.h
Unable to read source file /home/chun/GHRD/software/bootloader/u-boot-socfpga/arch/arm/include/asm/arch/boot0.h
S:0xFFFF0000 10,0 B reset ; 0xFFFF0084
+wait
+restore $sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
ERROR(ITR14-EXP17):
# in D:\board\cyclone_V_soc\GHRD\software\software\bootloader\debug-spl.ds:10 while executing: restore $sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
! "&__bss_end" is not a valid address
! Cannot take the address of the object
ERROR(CMD656): The script D:\board\cyclone_V_soc\GHRD\software\software\bootloader\debug-spl.ds failed to complete due to an error during execution of the script

Any ideas?

Reguards

[aikeu]

Hi CAlex,

The .ds file is referring to the debuger script where arm ds used during debugging run time.

Arm ds will read the script to perform the debugging steps example like setting breakpoint in the script in a function which you specify.

There are some example that shown in this document using hwlibs example like(Altera-SoCFPGA-HardwareLib-Timer-CV-GNU.tar.gz):

https://www.rocketboards.org/foswiki/Documentation/SoCEDS

https://www.rocketboards.org/foswiki/Documentation/SoCEDS

The MSEL selection is set as referring to page 8 of the document:

https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset02/soc-quickstart-v1.0.pdf

You mentioned that for once you successfully download the spl and initialize the DDR, that is shown on your UART with spl boot up logs?

Example for my case I program the image binary file(qspi-image.bin) which is a spl+application into the QSPI flash on address 0x000000: quartus_hps -c 1 -o pv -a 0x000000 qspi-image.bin

My board MSEL will set to boot from QPSI flash. Then application code will load into the DDR and run from DDR address starting 0x00100040

Anyway just for spl debugging there is this some example of running debugging using arm ds for cyclone V:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Debugging_U_45Boot

Thanks.

Regards,

Aik Eu

[CAlex]

The error occurs when I do the preload debug.

doing restore xxx/xx/u-boot-spl.dtb binary &__bss_end.

[aikeu]

Hi CAlex,

I do not have the similar .ds file in my folder directory of my baremetal application from the error you have shown.

I think the .ds script it trying to run but encounter error based on what is written in the script.

I would like to test it out with Arm ds. I will find a time to test on the board with arm ds next week.

At the mean time if used back the timer baremetal example in arm-ds, will it work?

Thanks.

Regards,

Aik Eu