Arria 10 soc configuration modes

[YuvalN]

According to the Arria 10 HPS system technical reference manual, configuring the fpga-fabric via the HPS supports an "early I/O release" mode.

My question: is this mode also supported when the FPGA fabric is configured by a non-HPS flash resource?

If the above is correct, it would imply that the HPS and fabric could be configured independently (in parallel) by different flash devices, and when HPS reaches the stage it requires DDR access (via the fabric's hard DDR controller) it would halt and wait until the fabric's "early I/O release" configuration stage (including the DDR controller) is complete, at which point the HPS boot sequence could resume.

Please advise

[mabdrahi]

Hi Yuval,

Sorry for my statement "For Aria10, its do not support (HPS and fabric could be

configured independently in parallel). This feature only exist old fpga design.".

for this feature it possible, but we do not have design example for Arria10

Thank youm

Aliff

[mabdrahi]

Hi Yuval,

do you have further question?

Thank you

[mabdrahi]

Sorry for my incorrect statement mention previously

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"For Aria10, its do not support (HPS and fabric could be

configured independently in parallel). This feature only exist old fpga design.".

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This feature is actually possible to get implemented, but we do not have design example for Arria10. We are sorry to inform you that you may have implement this feature by your self. we will try our best to support you.

[YuvalN]

Following out recent discussion, please review my summary below:

There are two relevant optional HPS/FPGA configuration flows:

1. Independent configuration, using two separate Flash memories, one for the HPS, then other for the FPGA. At this flow, the HPS starts booting, but when it requires accessing its DDR, it halts until the full (not just the "early I/O release" stage) FPGA configuration completion is flagged, and only then its DDR can be accessed and HPS init can complete.
2. Configure the FPGA by the HPS (via HPS Flash memory or memories). In this flow the HPS starts booting, performs a partial FPGA configuration, until "early I/O release" is flagged, and only then its DDR can be accessed and HPS init can resume. The HPS then completes also the 2nd stage of FPGA configuration, obtaining full FPGA configuration.

Did I get it right?

Regards,

Yuval

[mabdrahi]

Hi,

I will get back to you with the best answer

[mabdrahi]

Hi Yuval,

We do not have documentation for that.

how ever we can refer to this document

https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/early-i-o-release-fpga-configuration.html

[mabdrahi]

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