Custom board on Cyclone V HPS SDRAM preloader test

[BrianSune_Froum]

Dear Intel and all,

Apart from the DDR3 topology.
The first stage testing shows a very puzzling behavior.

BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 488 KHz
CLOCK: QSPI clock 2343 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
SDRAM: Ensuring specified SDRAM size is correct ...failed

[JingyangTeh_Altera]

Hi

What SDRAM Size that you are using?

Did you define the correct SDRAM size in the device tree as the sdram installed on the board?

Regards

Jingyang, Teh

[BrianSune_Froum]

@JingyangTeh_Altera 

I think this is caused by the fly-by routing.

There are two mt41k256m16.
But even I disassembled the far end die it is still not working properly.

Do there any way I can reduce the clock to 250M or 200M for sanity test?

I am so puzzling that with a 8 layer board on fly-by 50ohm and 100ohm design sill can't make things work?


  

[BrianSune_Froum]

@JingyangTeh_Altera 

New data

If I do in purposed and messed up the DLL of the DDR and force it to run 25MHz 256x16 is able to pass the test and even run the distro normally.

If I just remain the lower byte of the remain MT41K25616 DDR die it can pass the startup test as well and run 300MHz on C8 speed grade.

How could this even possible when lower byte can work but not both lower and upper byte?

Please do help 

[JingyangTeh_Altera]

Hi

Could you share a screenshot of all the DDR setting that you have currently made in the quartus project?

Regards

Jingyang, Teh

[BrianSune_Froum]

Hi,

First allow me to rephase the layout.

it is used fly-by and byte pin are swapped. i.e. DQ0-DQ7 <-> HPS DQ0-DQ7 is allowed to interchange any pins.
DQ DQM DQS are routed length matched.
All address are strictly followed no pin exchange and length matched.

Based on the above design which works on ZYNQ 7000 series.

The Qsys:

Board settings are not modified as EVM/EVB from other company work normally during development on software side and PL side do not modify those parameter as well.

[BrianSune_Froum]

@JingyangTeh_Altera 

Any news on this issue?

[khtan]

Hi Brian,

May I know what are the device tree settings for U-boot? Could you provide us the devicetree file that you're using?

Thanks

Regards

Kian

[BrianSune_Froum]

@khtan 

I think you are referring to the kernel dts?

For U-Boot I never touch it because I am using Quartus 18.1 

For that flow bsp-editor will create the MakeFile.

Once it runs make -all and make uboot

It will unzip the uboot zip from local install folder rather like newest FPGA device form GIT.

For kernel dts 

```

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright Altera Corporation (C) 2015. All rights reserved.

 */

#include "socfpga_cyclone5_b.dtsi"

//#include <dt-bindings/gpio/gpio.h>

/ {

model = "Custom Board Cyclone V Soc";

compatible = "altr,socfpga-cyclone5", "altr,socfpga";

aliases {

ethernet0 = &gmac1;

};

chosen {

bootargs = "earlyprintk";

stdout-path = "serial0:115200n8";

};

memory@0 {

name = "memory";

device_type = "memory";

reg = <0x0 0x20000000>; /* 512MB */

};

```

[BrianSune_Froum]

@khtan @JingyangTeh_Altera 

Original failed and forcing it run on 25MHz DDR die is MT41K256M16TW-107:P

Same bsp flow no dts modification no board settings changed.

As mentioned before Cyclone V HPS have no leveling so instead of using the full 32 bit two dies.
We only assembled one (lower data bus 0-15).

And the layout of the fly-by is lucky that the closest is low-data-bus die then high-data-bus die.
So if the farthest one is not populated and termination resistor should able to clean the remain traces.

FPGA -> DDR(0-15) -> DDR(16-31) -> Rtt
FPGA -> DDR(0-15) -> trace w/o any IC -> Rtt

Based on the above information:

We had tried another DDR die MT41K128M16JT-125:K and referencing the development board we got from other company.
They are using smaller one with page-size only 1k.

And we used low 300M setting on C8N device.

Result as follows:

After kept running it from cold to warm any every powerup will auto run 4 times to try boot but we clean out the uboot.img.
We cannot see any errors on "if (hps_emif_diag_test(SDRAM_TEST_NORMAL, 0, sdram_size) == 0)"
So why "MT41K256M16TW" could not works but "MT41K128M16JT" ??
Do the HPS EMIF have issue on page-size? 

Why development board component also use only 128x16 die rather than norm 256x16?

```

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

U-Boot SPL 2013.01.01 (Jul 30 2025 - 13:11:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 2343 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SDRAM: Ensuring specified SDRAM size is correct ...passed
SDRAM: Running EMIF Diagnostic Test ...Passed
ALTERA DWMMC: 0
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

```

[BrianSune_Froum]

@khtan @JingyangTeh_Altera 

This made us hard to believe that the EMIF is not buggy or there are some configuration is wrong.

See logs of DUT with MT41K128M16JT-125:K (single ide) fly-by layout board.
Under distro after boot stressapptest able to run continuously w/o crash drop or even halt. 
Please do internal engineer examine such issue.

brian@brian:~$ stressapptest
Log: Commandline - stressapptest
Stats: SAT revision 1.0.6_autoconf, 32 bit binary
Log: buildd @ bos02-arm64-001 on Thu Apr 5 10:35:12 UTC 2018 from open source release
Log: 1 nodes, 2 cpus.
Log: Defaulting to 2 copy threads
Log: Total 236 MB. Free 133 MB. Hugepages 0 MB. Targeting 200 MB (84%)
Log: Flooring memory allocation to multiple of 4: 200MB
Log: Prefer plain malloc memory allocation.
Log: Using memaligned allocation at 0xa9aff000.
Stats: Starting SAT, 200M, 20 seconds
Log: Region mask: 0x1
Log: Seconds remaining: 10
Stats: Found 0 hardware incidents
Stats: Completed: 12286.00M in 20.01s 614.02MB/s, with 0 hardware incidents, 0 errors
Stats: Memory Copy: 12286.00M at 614.19MB/s
Stats: File Copy: 0.00M at 0.00MB/s
Stats: Net Copy: 0.00M at 0.00MB/s
Stats: Data Check: 0.00M at 0.00MB/s
Stats: Invert Data: 0.00M at 0.00MB/s
Stats: Disk: 0.00M at 0.00MB/s

Status: PASS - please verify no corrected errors

brian@brian:~$ stressapptest -s 600
Log: Commandline - stressapptest -s 600
Stats: SAT revision 1.0.6_autoconf, 32 bit binary
Log: buildd @ bos02-arm64-001 on Thu Apr 5 10:35:12 UTC 2018 from open source release
Log: 1 nodes, 2 cpus.
Log: Defaulting to 2 copy threads
Log: Total 236 MB. Free 197 MB. Hugepages 0 MB. Targeting 200 MB (84%)
Log: Flooring memory allocation to multiple of 4: 200MB
Log: Prefer plain malloc memory allocation.
Log: Using memaligned allocation at 0xa9aff000.
Stats: Starting SAT, 200M, 600 seconds
Log: Region mask: 0x1
Log: Seconds remaining: 590
Log: Seconds remaining: 580
Log: Seconds remaining: 570
Log: Seconds remaining: 560
Log: Seconds remaining: 550
Log: Seconds remaining: 540
Log: Seconds remaining: 530
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Log: Seconds remaining: 30
Log: Seconds remaining: 20
Log: Seconds remaining: 10
Stats: Found 0 hardware incidents
Stats: Completed: 379246.00M in 600.24s 631.83MB/s, with 0 hardware incidents, 0 errors
Stats: Memory Copy: 379246.00M at 631.98MB/s
Stats: File Copy: 0.00M at 0.00MB/s
Stats: Net Copy: 0.00M at 0.00MB/s
Stats: Data Check: 0.00M at 0.00MB/s
Stats: Invert Data: 0.00M at 0.00MB/s
Stats: Disk: 0.00M at 0.00MB/s

Status: PASS - please verify no corrected errors

brian@brian:~$ stressapptest -s 600
Log: Commandline - stressapptest -s 600
Stats: SAT revision 1.0.6_autoconf, 32 bit binary
Log: buildd @ bos02-arm64-001 on Thu Apr 5 10:35:12 UTC 2018 from open source release
Log: 1 nodes, 2 cpus.
Log: Defaulting to 2 copy threads
Log: Total 236 MB. Free 197 MB. Hugepages 0 MB. Targeting 200 MB (84%)
Log: Flooring memory allocation to multiple of 4: 200MB
Log: Prefer plain malloc memory allocation.
Log: Using memaligned allocation at 0xa99ff000.
Stats: Starting SAT, 200M, 600 seconds
Log: Region mask: 0x1
Log: Seconds remaining: 590
Log: Seconds remaining: 580
Log: Seconds remaining: 570
Log: Seconds remaining: 560
Log: Seconds remaining: 550
Log: Seconds remaining: 540
Log: Seconds remaining: 530
Log: Seconds remaining: 520
Log: Seconds remaining: 510
Log: Seconds remaining: 500
Log: Seconds remaining: 490
Log: Seconds remaining: 480
Log: Seconds remaining: 470
Log: Seconds remaining: 460
Log: Seconds remaining: 450
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Log: Seconds remaining: 430
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Log: Seconds remaining: 400
Log: Seconds remaining: 390
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Log: Seconds remaining: 360
Log: Seconds remaining: 350
Log: Seconds remaining: 340
Log: Seconds remaining: 330
Log: Seconds remaining: 320
Log: Seconds remaining: 310
Log: Seconds remaining: 300
Log: Seconds remaining: 290
Log: Seconds remaining: 280
Log: Seconds remaining: 270
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Log: Seconds remaining: 250
Log: Seconds remaining: 240
Log: Seconds remaining: 230
Log: Seconds remaining: 220
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Log: Seconds remaining: 200
Log: Seconds remaining: 190
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Log: Seconds remaining: 170
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Log: Seconds remaining: 150
Log: Seconds remaining: 140
Log: Seconds remaining: 130
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Log: Seconds remaining: 90
Log: Seconds remaining: 80
Log: Seconds remaining: 70
Log: Seconds remaining: 60
Log: Seconds remaining: 50
Log: Seconds remaining: 40
Log: Seconds remaining: 30
Log: Seconds remaining: 20
Log: Seconds remaining: 10
Stats: Found 0 hardware incidents
Stats: Completed: 379550.00M in 600.24s 632.34MB/s, with 0 hardware incidents, 0 errors
Stats: Memory Copy: 379550.00M at 632.46MB/s
Stats: File Copy: 0.00M at 0.00MB/s
Stats: Net Copy: 0.00M at 0.00MB/s
Stats: Data Check: 0.00M at 0.00MB/s
Stats: Invert Data: 0.00M at 0.00MB/s
Stats: Disk: 0.00M at 0.00MB/s

Status: PASS - please verify no corrected errors

[BrianSune_Froum · Accepted solution]

The final result is that even with a fly-by routed topology there are no issue on both 1.5V and 1.35V DDR3 DDR3L.
The MT41K128M16  /w 1k page size shows no sanity issue on memtest stresapptest on distro.
UBOOT memory normal test also passed w/o any errors.

So after short testing we can only assume there are inherent bug on Quartus 18.1? or HPS IP.

No matter it is /w or /wo the board settings no drop no crash no stuck.

So the case ends here.

[JingyangTeh_Altera]

Hi

Sorry for the late reply, I was OOO the last week.

The fly-by topology is not supported for DDR3 in all Cyclone V and Arria V device

Regards

Jingyang, Teh

[BrianSune_Froum]

@JingyangTeh_Altera 

No your information is only based on words of the documents.

But what altera reference had done is violated what the document said.

Can you see the image attachment?

https://community.intel.com/t5/Programmable-Devices/Custom-board-on-Cyclone-V-SoC-HPS-SDRAM-topology-unclear/m-p/1703953#M100767

I am completely lost and so confused with the actual hardware result (not simulation not just theory level).

What we had tried is also mentioned in that ticket.

If leveling is not allowed then it is supposed to fail no matter how on the fly-by /w two die in fly-by layout.

But results are not align it can passed all stress test with thermal profile 60 degree so fast slow corner are all passed.

The only differences are the DDR3 die is 1K page or 2K page in previous fails.

[JingyangTeh_Altera]

Hi

Yeah, sometimes the board is able to perform better than it suppose too.

The results you are seeing might differ from board to board.

That could be why the document stated that it is no supported.

We could not guarantee any performance issue if you are using the device out of the supported specification.

Regards

Jingyang, Teh

[BrianSune_Froum]

@JingyangTeh_Altera 

I think you had misread my descriptions on previous post.

What I am pointing out it that the official development board from altera itself already violated the design rules.
If leveling is not supported then as you mentioned clearly it is not allow to use fly-by from first place.
But according to the allegro design file from the board design.

With this image of the official altera design layout. it already violated the Balance-T design.
There is a ECC at one end but not middle and it does not follow a T branch design but a fly-by hybird layout.

So please explain why this is the case.

[BrianSune_Froum]

@JingyangTeh_Altera @khtan 

Final solved the 2K pagesize problem for 2K the precharge time is critical on the settings.

Same Quartus 18.1 just need to tune the parameters more tediously.

And also even w/o the leveling as datasheet mentioned. There are no issues on fly-by design.

Finally saved the batch.

And this info should help other designers until 2030.

[SueC_Altera]

This is great news, Brian! Thanks for sharing your solution.

Sue

[JingyangTeh_Altera]

Hi

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh