Cyclone V DDR3 SDRAM timing configuration missing in handoff files

[PeterTs]

My query relates to SDRAM timing and skew parameters modified in platform designer that (after generation, FPGA rebuild and create BSL script) do not appear in the handoff files.

We have a PCB with a Cyclone V SoC FPGA (5CSXFC6C6U23I7) and the HPS interfacing to a single 4Gb DDR3 SDRAM device (EltronTech EM6HE16EWAKG). We are using the uboot SPL as the preloader (v2021.10).

On running the preloader SDRAM calibration fails at the calibration write stage.  So we assume there is some issue with the skew between CK and DQS. The CK traces are slightly shorter than DQS, with CK about 20 ps shorter).

To address this, we have tried to adjust some of the SDRAM board skew settings in Platform Designer. We then successfully run generate HDL, then rebuild the FPGA and programming files to produce HPS handoff files, execute the create BSL script, rebuild and execute uboot SPL, there is no change observed in the debug output (debug level 2 is enabled in sequencer.c).

Indeed, the handoff files are identical across SDRAM timing changes.

On inspection, it appears that only a subset of the SDRAM timing parameters make it into the emif.pre.cml and sdram_config.h files (tMRD, tRAS, tRCD, tRP, tREFI, tRFC, tWR, tWTR, tFAW, tRRD and tRTP). 

My questions are:

- What happens to the other settings such as tDQSCK and the board skew parameters such as Maximum CK delay to DIMM, Maximum DQS delay to DIMM, Max and Min delay difference between CK and DQS, etc?

- Are they set in the SDRAM controller somehow? Should they be - is this even possible?

- What should be done to ensure these parameters are used?

- Failing the above, is there some other way to make timing adjustments to ensure successful SDRAM calibration?

I've added screenshots of the platform designer SDRAM timing settings forms and sdram_config.h for reference.

[JingyangTeh]

Hi

I am Jingyang. Please give me sometime to take a look at files and get back to you.

Regards

Jingyang, Teh

[PeterTs]

Hi Jingyang,

We have since found the cause of the SDRAM failing to complete calibration: an error in the PCB layout has the SDRAM BA1 and BA0 swapped between the Cyclone V and the SDRAM chip. As a result, the commands for the SDRAM mode registers 1 and 2 will also be swapped.  As it doesn't look possible for the bank address pins to be reassigned in software, the crossed signals have been corrected by a hardware modification to the tracks (on inner PCB layers, so not easy!) and the SDRAM now completes successfully.

It would still be interesting to know whether SDRAM board skew and other SDRAM timing settings made in Platform Designer are used by the HPS.

Peter

[JingyangTeh]

Hi Peter

Glad that your problem is solved.

The values of the Platform Designer is used by the HPS through the handoff files.

The values of the platform designers are exported as an xml files in the "hps_isw_handoff\soc_system_hps_0" in the quartus project folder.

Then while building the bootloader we will need to run a script which is the "cv_bsp_generator.py script".

This script will generate a few header files in which is used to compiled together with the bootloader.

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Boot_from_SD_Card

Regards

Jingyang, Teh

[JingyangTeh]

HI

Do you have any following up question for this case?

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome to reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Regards

Jingyang, Teh