Cyclone V HPS bus - FPGA-to-SDRAM

[BrianSune_Froum]

Dear Intel, and all,

Brian here and there is a very puzzling documenting on:

https://www.intel.com/content/www/us/en/docs/programmable/683360/18-0/fpga-to-hps-sdram-access.html

Based on the 256 bit and # of allowed master to interact with the controller.

Why 256bit support 4 but 32bit only 1 at the same time?

Meanwhile, on the qsys design the behavior is completely reversed.

To achieve the maximum throughput I assume the 256bit is formed by the DDR3 quad DDR 32bit = 4*2*32 = 256.
Then the data either used band or page hit method to burst out.

So the 256 can split into 4x64 2x128  or 1x256 W/R calls.

Please FAE or internal staff confirm the above info is wrongly labeled?

[ShoH_Altera]

Hi @BrianSune_Froum ,

Thanks for you posting.

First, Let me confirm how FPGA-to-SDRAM bridge can be configured.

"There is a maximum of six command ports, four 64-bit read data port and four 64-bit

write data port."

These three types of ports can be combined to form multiple Avalon-MM/AXI interfaces. 

The table 5 to which you refer shows which ports and how many are required for each interface.

For example : You can configure

  1x  64bit AXI  (2:CommandPorts, 1:ReadPort, 1:WritePort)

  1x 128bit Avalon-MM Write Only (1:CommandPort, 0:ReadPort, 2:WritePorts)

  1x 128bit Avalon-MM Read Only (1:CommandPort, 2:ReadPorts, 0:WritePort)

  1x  64bit Avalon-MM Bidirectional (1xCommandPort, 1xReadPort, 1xWritePort)

The above configuration utilizes 4:CommandPorts, 4:ReadPorts, 4:WritePorts. (2:CommandPorts are un-used.)

Is there something strange or wrongly labeled?

Regards,

[BrianSune_Froum]

@ShoH_Altera 

With all due respect you had misinterpret my question.

The question is not above how to confirm.

It is above AXI3 settings the table from the document links are possibility wrongly labelled.

Perhaps you are try it using Quartus.

For AXI3 256 bit width bus how many interface can you used?

128 bit and 64 bit.

The question is still opened.

[BrianSune_Froum]

Dear Intel, and all,

Additional info:

Encourage employee @ShoH_Altera read document before laying down info that is not align with Intel pro

prosing?

https://www.intel.com/content/www/us/en/docs/programmable/683360/18-0/fpga-to-hps-sdram-access.html