Intel® SoC FPGA Embedded Development Suite
Support for SoC FPGA Software Development, SoC FPGA HPS Architecture, HPS SoC Boot and Configuration, Operating Systems
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Cyclone V SoC Unused Pin

btmoreau
Beginner
331 Views

Hello,

I am attempting to design a PCB based around an Intel Cyclone V SoC and am struggling to figure out the unused pin connectivity. The Intel Pin Connection Guideline for the DIFFIO_TX pins directs me to "Connect unused pins as defined in the Quartus Prime software." and I have configured the unused pins in Quartus to be "As Input Tri-Stated with Weak Pull-up" but I'm not sure how to implement that in the actual PCB schematic. I am assuming I can leave the pin floating as it with be internally pulled up to the IO VCC and the SoC shouldn't be using it for any logical input but I would like someone to confirm this or direct me to any resources that could help me confirm this.

 

Thank you for your help and have a nice day!

 

-Bradley

0 Kudos
1 Solution
2 Replies
btmoreau
Beginner
254 Views
Reply