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DDR3 Board parameters

ramsoffer_123
New Contributor I
656 Views

Hi Everyone,

Im working on a cyclone V device with DDR3 MICRON vendor.

we are now trying to fill up the board parameters in the setup and hold derating section.

ramsoffer_123_0-1712933184208.png

we have some board simulation data from the board designer layout but we don't sure what value to take. 

The tis,tih,tds,tdh in the simulation output are margin from the minimum setup and hold.

Do we need to add this margin value to ddr spec tis and tih ?

tis,tih: 

ramsoffer_123_1-1712933362294.jpeg

tds,tdh:

ramsoffer_123_2-1712933405688.png

thanks for your answer in advance,

BR,

Ram.

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zhenruan
Employee
595 Views

Hi Ram,

 

Please refer to the link below for the settings:

https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/slew-rate-setup-hold-and-derating-c.html

 

Regards,

Aaron 

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ramsoffer_123
New Contributor I
530 Views

hi,

it helps.

still working on it.

 

thanks,

BR,

Ram.

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WZ2
Employee
318 Views

Hi there,


I wanted to check if you have any further questions or concerns. If not, I will go ahead and mark this issue as resolved.


Additionally, we would greatly appreciate it if you could take a moment to fill out our survey. Your feedback is valuable to us and helps us improve our support quality.


Thank you for your time and cooperation.


Best regards,

WZ



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