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Error while running SPL debug bootloader script

eng6138
Novice
628 Views

Environment:  Ubuntu 20.04, Arm DS 2020 Standard, Quartus Prime 18.0 Standard, Terasic DE1-SoC dev kit.

Reference page:  https://rocketboards.org/foswiki/Documentation/SoCEDS#Cyclone_V_Bare_Metal_Example_Using_SoC_EDS_Sta...

Issue:  running the "debug-spl.ds" script noted in the link above (but tailored for the DE1-SoC dev kit), DS 2020 reports "ERROR(CMD360)...Wait for stopped timed out".  u-boot built successfully, as did the Quartus project which is based on a Terasic reference design.  I can run generic "hello world" programs, but cannot load the custom bootloader which allows access to the FPGA components.  debug-spl.ds script:

stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off
loadfile \$sdir/u-boot-socfpga/spl/u-boot-spl 0x0
start
wait
restore \$sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
tbreak spl_boot_device
continue
wait 60s

From the DS 2020 Commands window:

Connected to running target Intel SoC FPGA - Cyclone V SoC (Dual Core)
cd "[...]/developmentstudio-workspace"
Working directory "[...]/developmentstudio-workspace"
source /v "/opt/arm/developmentstudio-2020.0/sw/debugger/configdb/Scripts/altera_target_check.py"

No SYSID registers could be found. Has a peripheral description file been supplied?

source /v "[...]/Documents/DE1_SoC_demo_2020/software/bootloader/debug-spl.ds"
+stop
Execution stopped in SVC mode at S:0xFFFF29B8
S:0xFFFF29B8 B {pc} ; 0xffff29b8
+wait 5s
+reset
+stop
WARNING(CMD315): Target is not running
+wait 5s
+set trust-ro-sections-for-opcodes off
Target has been reset
+loadfile \$sdir/u-boot-socfpga/spl/u-boot-spl 0x0
WARNING(IMG66): Unable to check the image is the correct endianness as the target is running.
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFFA7FB (size 0xA7FC)
Loaded section .rodata: S:0xFFFFA7FC ~ S:0xFFFFCEAA (size 0x26AF)
Loaded section .data: S:0xFFFFCEAC ~ S:0xFFFFCF0B (size 0x60)
Loaded section .u_boot_list: S:0xFFFFCF0C ~ S:0xFFFFD6AF (size 0x7A4)
Entry point S:0xFFFF0000
Execution stopped in SVC mode due to a breakpoint or watchpoint: S:0x00000000
S:0x00000000 LDR pc,[pc,#24] ; [0x20] = 0xA8
+set semihosting enabled true
Semihosting server socket created at port 8000
+start
Starting target with image [...]/Documents/DE1_SoC_demo_2020/software/bootloader/u-boot-socfpga/spl/u-boot-spl
Running from entry point
WARNING(CMD399-COR168):
# in [...]/Documents/DE1_SoC_demo_2020/software/bootloader/debug-spl.ds:12 while executing: start
! Failed to start the target
! No function named "main" could be found
WARNING(CMD407): Trying the entry point instead
Execution stopped in SVC mode at S:0xFFFF0000
In boot0.h
S:0xFFFF0000 10,0 ARM_VECTORS
+wait
+restore \$sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
Restoring Binary file [...]/Documents/DE1_SoC_demo_2020/software/bootloader/u-boot-socfpga/spl/u-boot-spl.dtb into memory
Restoring section S:0x00000000 to S:0x00000A9D into memory S:0xFFFFD6C4 to S:0xFFFFE161
+thbreak spl_boot_device
Hardware breakpoint 2 at S:0xFFFF0B0C
on file spl_gen5.c, line 31
+continue
+wait 60s
ERROR(CMD360):
# in [...]/Documents/DE1_SoC_demo_2020/software/bootloader/debug-spl.ds:26 while executing: wait 60s
! Wait for stopped timed out
ERROR(CMD656): The script [...]/Documents/DE1_SoC_demo_2020/software/bootloader/debug-spl.ds failed to complete due to an error during execution of the script

 

0 Kudos
5 Replies
EBERLAZARE_I_Intel
534 Views
eng6138
Novice
525 Views

You linked me to the same webpage I linked and followed in the original post.  Really?  After 2 months of waiting?

EBERLAZARE_I_Intel
505 Views

Hi,

The step I am referring to is to debug where it last stopped, did you try running the DS-5 step by step and check where it last stop is? Is it SDRAM.c etc? 

You may want to try with our GHRD image to see if this would boot:

https://releases.rocketboards.org/release/2020.07/gsrd/cv_gsrd/

 

ESaiv
New Contributor I
283 Views

I think I can help. Check out my written solution on my own post which had the same problem as you're having. Since you are using the DE1, not Cyclone V Development Kit, I bet it's the same problem as me. I was using the DE10-Nano. 

 

Let me know if I can clarify anything in my solution post for you. 

 

[Edit a few hours later: I noticed in your post that I misread, and that you did in fact tailor the process for your DE1-SoC kit. My fix might not be much use then. Did you you do all three steps? Hand-off, qts_filter, and the config?]

ESaiv
New Contributor I
280 Views

And just to be clear, in my post I linked above, I mention the Bare Metal User Guide, but go ahead and completely ignore that. What I typed as my solution applies to the SoCEDS example you linked as well. I reference this example in my post as well.

Reply