How to customize the Agilex 7 I-series OS build with SOF and HPS changes ?

[sujan19]

Hi Team,

So we are working with Agilex 7 I-series Evaluation kit, We have successfully built yocto image for the GSRD as explained in this guide : https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/i-series/soc/gsrd/ug-gsrd-agx7i-soc/#set-up-yocto

And the board boots up fine, and tested the led example applications as well. 

Now we want to add our own SOF exported from Quartus Prime Pro design and re-build the OS. 

NOTE: The Quartus design may contain some interrupts, msgDMA, and GPIO's.

I have a few questions: 

1. Apart from the SOF file, what other file needs be generated from Quartus Prime ? 
2. Where is the dts, which we can customize for HPS & FPGA-HPS ? 
3. What's the build flow for such a customized design. Since the guide only explains about the GSRD,  Can you explain the flow for custom designs ? 
   
   

Regards,
Sujan

[JingyangTeh_Altera]

Hi

You could take a look at the link below for the GSRD for the Agilex7 I series devkit.

https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/i-series/soc/gsrd/ug-gsrd-agx7i-soc/

Please find the answers below:

1.Apart from the SOF file, what other file needs be generated from Quartus Prime ? 

For sof it is a volatile configuration. For a non-volatile configuration you would need the RBF or JIC format.

2.Where is the dts, which we can customize for HPS & FPGA-HPS ? 

For the Agilex7 you could find the device tree here:

https://github.com/altera-fpga/linux-socfpga/tree/socfpga-6.12.11-lts/arch/arm64/boot/dts/intel

3.What's the build flow for such a customized design. Since the guide only explains about the GSRD, Can you explain the flow for custom designs ? 

You could refer to the link below for the boot flow:

https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/f-series/soc/boot-examples/ug-linux-boot-agx7-soc/

Regards

Jingyang, Teh

[sujan19]

Hi Jingyang, 

Thanks for replying.

You could refer to the link below for the boot flow:

https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/f-series/soc/boot-examples/ug-linux-boot-agx7-soc/

1. This Guide for GHRD is for f-series SOC, does this apply for I-series as well? 
2. And correct me if i am wrong, should we use our custom design's SOF file to build the ghrd.hps.jic image in this command : 

quartus_pfg -c \
agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof \
ghrd.jic \
-o device=MT25QU128 \
-o flash_loader=AGFB014R24B2E2V \
-o hps_path=u-boot-socfpga/spl/u-boot-spl-dtb.hex \
-o mode=ASX4 \
-o hps=1​

instead of one built by this git repo : https://github.com/altera-opensource/ghrd-socfpga 

• If yes, what other file do we need to generate apart from SOF file to generate .jic and .img files ? 
• We also have this file hps_bootloader_handoff_bringup.bin , what is use of this ? and where is it used ? 

Regards,
Sujan

[JingyangTeh_Altera]

Hi

Yes. The steps for building are the same for the I Series and F series.

If you have created your own custom design you can use your own custom sof instead of the GSRD.

It is recommended to try out the GSRD to understand the over all flow before running your own design.

Besides the Hardware Design, you would also need the SPL, Bootloader, rootfs, Device Tree and Linux Image.

u-boot.itb

socfpga_agilex_socdk.dtb

Image

core-image-minimal-agilex7_dk_si_agf014eb.rootfs.tar.gz

In general these are the required file to boot into the linux environment.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Did you managed to go through the materials shared?

Do you have any follow-up questions?

Regards

Jingyang, Teh

[sujan19]

Hi, 

Yes i went through the resource, looking fine till now. 

As u previously mentioned that the dts file is in : https://github.com/altera-fpga/linux-socfpga/tree/socfpga-6.12.11-lts/arch/arm64/boot/dts/intel

Which file to be exact, from the resource it seems that its this : 

• linux-socfpga/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb

But this is compiled dtb, where is the source of this dtb, And this is only for PS side, if I'm not wrong. 

Where is the one for pl for ex: In Xilinx FPGA's  its pl.dtsi & system-user.dtsi (for PL to PS conf). 

Can you let me know the intel equivalent of these dts ? 

Regards,
Sujan

[sujan19]

Hi, 

I found this guide for FPGA to HPS bridges for linux : https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/f-series/soc/setup-use-bridges/ug-setup-use-bridges-agx7f-soc/

Shouldn't we follow this procedure not the linux boot examples, when our design contain Bridges like msgDMA , pio & interrupts ?

Regards,
Sujan

[sujan19]

Hey @JingyangTeh_Altera , 

Any update ? 

Regards,
Sujan

[JingyangTeh_Altera]

Hi

The device tree you are looking at is the one below:

https://github.com/altera-fpga/linux-socfpga/blob/socfpga-6.12.11-lts/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts

The "FPGA to HPS bridges for linux" that you have found is a example design that is built on top of the GSRD shared.

The example design shows the connection needed for msgdma where as the GSRD shows only the basic IO function and linux boot only.

Regards

Jingyang, Teh

[sujan19]

Hi 

I was able to build the image with our design successfully. 

I had to write the device tree manually for our custom pl design. Is there any other way to do this ? (I know that sopc2dts is old and not supported anymore, is there any alternatives ? )

Also last thing, we are working with msgDMA, and i was trying to find the character device driver for userspace : 

 recipes-drivers/msgdma-userio/msgdma-userio.bb

as mentioned here : https://www.intel.com/content/www/us/en/docs/programmable/768979/2023-3-1/yocto-recipe-recipes-drivers-msgdma.html

But can't seem to find it anywhere, can you let me know, if there is any userspace msgDMA driver we can use or do i have to write one ourselves ? 

Regards,
Sujan

[JingyangTeh_Altera]

Hi

You would need to manually create the dts.

The peripherals node have been created, you would need to enable or disable it base on your usage of the hard IO.

There are samples based created for the devkit.

For the msgdma driver, you could get the driver here:

https://github.com/altera-fpga/linux-socfpga/blob/7b497655d942b6a44a87a2367463967e433ad422/drivers/net/ethernet/altera/altera_sgdma.c#L4

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Do you have any follow up question on this issue?

Regards

Jingyang, Teh

[sujan19]

Hi,

No, that's all you can close this thread. Thanks for your support .

Regards,
Sujan

[JingyangTeh_Altera]

Hi

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh