I am in the middle of trying out Intel FPGA starter edition 10.5b, however I can not get modelsim to display my unpacked array signal in the systemverilog. The simulation works fine but vsim does not even list the signal in the Objects window.
Below is an example of unpacked array:
logic [7:0] my_unpacked_array;
Please provide your code & screenshot of simulation window, Its difficult to support without code & result.
Are you unable to see the unpacked array signals in Objects window?
Thank you Vicky!
I managed to get support from Mentor and found out what the issue is.
I normally uses wild character * to log everything. This somehow does not work with unpacked array. I have to individually log them one by one in order to debug them in the waveform (when running simulation in command line)