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matif
Novice
463 Views

Inconsistent Data of Transceiver

​Hi all, I am printing my data from trasnceiver at UART output terminal (putty). My setup consists of a counter running at 100 Mhz. this counter is connected  to transciever. The transceiver pll clock is also 100 MHz. Now when I try to print my coutner data which i received back in serial loopback of the transciever onto the ARM UART terminal. I am running Linux on arm. I have cyclone V Arrow Sockit board. Now my data is inconsistant like I am receiving 1,4,4,12,12,4,3,6,7,12,14,.... but I wana see consistent counter sequence like 1,2,3,4,5,6,7,...,15.

 

Any help please? 

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23 Replies
CheePin_C_Intel
Employee
112 Views

Hi,

 

As I understand it, you seems to observe some issue with RX parallel data output display at UART output terminal. 

 

By the way, I notice that you have filed another case 04274469, just would like to check with you if both of the cases 04274469 and 04274941 are similar? If they are the same, then we could follow up using a single case for better tracking purpose.

 

Regarding your RX parallel data output issue, we would require further debugging to further narrow down the issue. Just would like to check with you on the following:

 

1. Just wonder if you have had a chance to SignalTap the transceiver RX parallel data output to see if the output is something expected?

 

2. You may also cross check the SignalTap data with the UART terminal to see if there is any discrepancy.

 

3. Would you mind to share with me your transceiver Native PHY's .qsys file so that I can have a better understanding on your transceiver configuration.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

matif
Novice
112 Views

• Hi Chee Pin, Thank you so much for your reply. 1. Yes case 04274941 and 04274469 are the same cases. Actually I wasn't getting a responce thats why I filed another similar case with more details. 2. Yes, I have issues with RX Parallel Data output display at Uart output terminal. I want to see the consistent counter sequence like 0,1,2,3,4, upto 14 but as you can see in my post I am getting inconsistant data. Some of the people suggested me that because I am running Linux on my cyclone V board that is why my application reading rate is really slow but I also tried to run the counter at really slow speed like at just 10 Hz but even then I was not getting the consistent data. To be sure that the transceiver is synchronized, I connected the rx_syncstatus output to one of the LED on board and the LED is lighted up means transceiver is synchronized. 3. Yes, for sure, I can share with you my quartus project file so that you can have a look. Where should I share it because I am not able to upload the file here at website remember last time we also tried to upload the transciever loopback example and it didn't work so you had to email me the file. So just let me know how can I share my transciever file with you. And thank you so much for your reply. You always help me. Appreciated. Regards   Sent from Mail for Windows 10
CheePin_C_Intel
Employee
112 Views

Hi,

 

Thanks for your update and clarification. Seems like both the case get routed to me at the same time yesterday. I will set the 04274469 to close and we shall continue to follow up using this case.

 

Let's try to debug and isolate any potential issue at the transceiver level first before proceed to UART. If required, I will further engage UART expert for further assistance.

 

Would you mind to signaltap the Native PHY's status signals for me? This include reset, rx_is_lockedtoref, rx_islockedtodata, tx/rx_ready and the RX parallel data. This would be helpful for me to check if there is any anomaly as well as to check on the RX parallel data output at the Native PHY directly.

 

You may try to attach your signaltap file and the test design QAR directly to the Forum if it is something OK to viewing by public. My previous experience is that customer who open the Forum case can attach/upload file. Only me cannot attach to the thread. The server will prompt me some permission error. If the files are confidential, please feel free to let me know, I will drop you an email for sharing.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

matif
Novice
112 Views

Hi Chee Pin, Thank you sooooooooooooooo much for your support. I tried but unfortunately the Forum is not allowing me to attach any files. I even tried using different web browser but not successful. And I am really sorry I don’t know how to use signaltap tool of the quartus because I have never used it. Actually I don’t have a USB blaster cable with which I can use Signaltab tool so I always use model sim to check some simulations and then use raw binary files to program my FPGA on board. But for your convinience, I have extracted These Signals at the modular Level and added as many comments in my HDL design as possible. I have emailed you the files at your email address so that you can check. I am also sending you my .c file and a screenshot of my UART Settings because I have the Feeling that there is some Problem on the UART side. Thank you again for your support. Regards… Sent from Mail for Windows 10
CheePin_C_Intel
Employee
112 Views

Hi, Thanks for your update. Sorry for the inconvenience with the Forum file upload. I understand that you do not have a USB blaster cable. Just would like to check with you if you are using any of our devkit or your own board? Without signaltap, it would be rather difficult to check on the Native PHY’s parallel data output. I understand that you have run through Modelsim simulation with your XCVR design which I believe there is no issue in your simulation. I have not yet received your test design files in my email. I will wait for them then further look into it. By the way, just wonder if you have tested sending fix data pattern (not incremental counter value) to the UART to see if you can see the right data? You can try with a few different fix data pattern. With this, we can further check on the functional and isolate any potential timing related issue. Thank you. Best regards, Chee Pin
matif
Novice
112 Views

Hi...

thanks for the reply. I am using Arrow Sockit Board with (cyclone V SoC chip 5CSXFC6D6F31C8). I have already emailed you the files. I am really sorry about the signal tap but the problem is that I dont know how to use it.

I shall try sending a fix pattern over the transceiver and see the result.

Thank you so much again for the support

CheePin_C_Intel
Employee
112 Views

Hi, Can you share with me a link to the Arrow Socket Board on web? I would like to take a look to see if we can use Signaltap with it. Thank you. Best regards, Chee Pin
CheePin_C_Intel
Employee
112 Views

Hi,

 

Thanks for sharing the info on the Arrow SocKit eval board. For your information, as I look into the start guide (https://rocketboards.org/foswiki/pub/Documentation/ArrowSoCKitEvaluationBoard/SoCKit_Getting_Started...) , I notice that the board has built in USB Blaster II. You can refer to the Figure 3-5 USB and Power Cables. It is a microB USB connector. Generally if you directly connect a USB cable to this, your Quartus will be able to detect and program the CV device through JTAG. You can use SignalTap with this USB Blaster II. Just would like to check with you how do you program the CV device currently?

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

matif
Novice
112 Views

Hi,

Thank you so much for your message. Oh I didn't know that the board has a build in USB blaster 2. Thanks a lot for letting me know. So that means that I take a usual USB cable, connect it to the USB Blaster 2 port and my quartus software will be able to detect it.

For now, to program my CV device, I convert my project.sof into project.rbf (raw binary file) using quartus software. Then I copy this project.rbf file into the fat partition of a micro SD card. Then I plug this MicroSD card into my CV device board. I then use uboot to program my CV device. It's a really time consuming and lengthy process because I have to remember many uboot script commands to program my CV device.

Thanks a lot again, I shall try this microUSB port to check if it is working as a USB blaster port? Thanks a lot again..

matif
Novice
112 Views

Thanks a lot. Just checked. The usb blaster is working. Thanks a lot again. Now I can use SignalTap with this USB blaster II. Thanks a lot again for your support. I shall Keep you inform of further Progress. Sent from Mail for Windows 10
CheePin_C_Intel
Employee
112 Views

Thanks for the update. Glad to hear that the USB blaster is working. Please feel free to keep me posted on the RX status and RX Parallel data check in signaltap. Thank you. Best regards, Chee Pin
CheePin_C_Intel
Employee
112 Views

Hi,

 

Just would like to follow up with you on this. Thank you.

matif
Novice
112 Views

Hi,

Thanks again so much for your support and help. I just tested my design on signal tab logic analyzer. I noticed that the data sequence is perfectly fine. I have also emailed you the design files together with signal tab logic analyzer file so that you can also have a look. The transciever signals like rx_syncstatus and rx_pattern detect are also working fine. Now I am confident that my HDL design is all working fine.

But I still have issues with printing of inconsistent data on UART output terminal. I have the feeling that to display my data on UART terminal, I need to make a whole soc_system which requires to incorporate HPS into the design. Now I utilised Qsys tool in Quartus software to connect my HDL design with HPS. Now my transceiver's pll clock is 62.5MHz. I am running Linux on my HPS. So that means the Linux application that I wrote for the HPS to print my transceiver received parallel data onto the UART terminal is running on much lower clock than that of my transceiver's pll clock. Is it possible to involve an UART terminal expert who can help us in this issue?

CheePin_C_Intel
Employee
112 Views

Hi,

 

Thanks for sharing the files. As I look into the SignalTap file, yes, your understanding is correct. Your XCVR design is working fine, all ready signals asserted, RX achieved sync and RX parallel data output is correct.

 

We will need to further engage our UART expert to provide further assistance. I will try to see if I can duplicate a case and route to UART team. If not, I will let you know to seek your help to open a new case so that I could route it.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

 

CheePin_C_Intel
Employee
112 Views

Hi,

 

It seems like I am unable to duplicate a case from my side. Would you mind to help open a new case and add your latest note to the case as description? Please feel free to let me know the case number so that I could help to expedite the routing.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

 

matif
Novice
112 Views

​Hi,

Thank you so much for your support and help. I have created a new case here

https://forums.intel.com/s/question/0D50P00004PYXunSAH/inconsistent-data-on-uart-output-terminal-fro...

 

 

CheePin_C_Intel
Employee
112 Views

Hi, Thanks for your help. I have notified our UART team to expedite the routing. Please let me know if it is still not routed by mid of tomorrow. Thank you. Best regards, Chee Pin
matif
Novice
112 Views

Thank you so much for your support. I really appreciate your help. I shall keep you informed of the progress.

matif
Novice
57 Views

Hi. the Uart team didnt contacted me yet

 

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