On Cyclone-V, how do I configure a pin mux to use the DIFFIO_RX_B46P pin as a general purpose IO pin?

Intel® SoC FPGA Embedded Development Suite

Support for SoC FPGA Software Development, SoC FPGA HPS Architecture, HPS SoC Boot and Configuration, Operating Systems

On Cyclone-V, how do I configure a pin mux to use the DIFFIO_RX_B46P pin as a general purpose IO pin?

722 Views

Link Copied

1 Reply

536 Views

Hi Thomas,

You may do so in pin assignment editor in Quartus.

Thank You.

Copy link

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.