PMBUS Error During Configuration on Generated Example Design

[RLambdin92]

Currently attempting to run the example Low Latency Ethernet 10G MAC on the Stratix 10 SX SoC H-Tile (1SV280HU2F50E1VGAS) devkit. I've generated the example design as stated in the Low Latency Ethernet 10G MAC Intel Stratix 10 FPGA IP Design Example User Guide. Working to try and load this design onto the above board but am running into an error shown on the image attached. This has been tested on two different H-Tile Stratix 10 devkits and the same issue occurs both times.

I've attempted to load other designs which I've been told previously worked on these devkits and I am continually getting this error. This includes a previous iteration of the LL Ethernet 10G MAC design from a previous developer. I've spent some time looking at specific issues and off shoot solutions I've seen on Google but to no avail. Looking for some assistance pinning down what potentially is going on (whether its a board issue, a programmer issues, design issues, etc). Appreciate any assistance!

[Fakhrul]

Hi RLambdin92,

You may find your solution in this similar thread here:

Solved: Re: stratix 10 PMBUS's issue

Another thing, have you verified the VID setting appropriately? Refer here:

Intel® Stratix® 10 Power Management User Guide

There is a few KDBs related to this error:

https://www.intel.la/content/www/xl/es/support/programmable/articles/000087531.html

https://www.intel.com/content/www/us/en/support/programmable/articles/000075102.html

Regards,

Fakhrul

[Fakhrul]

As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.