Pins

[K606]

What is the limit on how many pins can be used between the HPS and FPGA? Is there any availability for custom pin definitions here?

Thanks,

K

[SueC_Altera]

Hi K606,

Can you be more specific about what device you are using, whether you are routing from the HPS to the FPGA or FPGA to HPS?  Have you done a google search on this question?

Sue

[K606]

Hi there,

Sorry yes forgot to mention - it is the Agilex 5.

Ideally both directions - so for I have seen some docs on the register map, but these are all pre-defined pins. Are there any open ones?

[SueC_Altera · Accepted solution]

Hi K606,

Please refer to this document: https://www.intel.com/content/www/us/en/docs/programmable/813934/24-3/general-purpose-i-o-overview.html and see if it answers your questions.

Sue

[BoonBengT_Altera]

Hi @606,

Greetings, as solution has been marked from the mention doubts, hence would assume challenge are overcome. 

Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes

BB