Puzzling AXI3 protocol signal capture during HDL development.

[BrianSune_Froum]

Dear Intel and all,

Could FAE or internal HPS or any stuff can help check if this is even possible?

Can bvalid bresp return at the middle of the burst write?

I think this is a violation of AXI3 protocol?

Thank you

[BrianSune_Froum · Accepted solution]

Sorry for the noise. After debug it is a bead missing trigger a chain shifting on the bus.