Intel® SoC FPGA Embedded Development Suite
Support for SoC FPGA Software Development, SoC FPGA HPS Architecture, HPS SoC Boot and Configuration, Operating Systems

SD Card Boot

malcolm_locke
Novice
1,535 Views

Hi,

 

I have an Agilex 5 Modular Development Board which I can boot with the supplied SD Card.

I have tried to update to the latest image at Index of /2025.04/gsrd/agilex5_mk_a5e065bb32aes1_gsrd/,

 

However, after programming an SD Card with this image, as far as I can tell, my board doesn't boot. I get no output from the serial port so I don't have any way of debugging.

 

Please can you help with any advice how to proceed to diagnose what is going wrong?

 

Many thanks

Malcolm

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Jeet14
Employee
1,386 Views

Hi Malcolm,


I hope you have reprogrammed the new .jic image to QSPI before using the sd card image.

This .jic image is given on the same link-https://releases.rocketboards.org/2025.04/gsrd/agilex5_mk_a5e065bb32aes1_gsrd/


Please confirm.


Regards

Tiwari


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malcolm_locke
Novice
1,298 Views

Hi Tiwari,

 

Many thanks for your answer. After programming the QSPI with the image you suggested, I was able to boot linux successfully ( I believe from the SD Card!).

 

Please can you give a brief explanation as to why this was necessary? What was preventing linux from booting?

 

Many thanks

Malcolm

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JingyangTeh_Altera
1,197 Views

Hi Malcolm


This could be due to the mismatch in the hardware design.

For the the Hardware Design in the GSRD, it is HPS first configuration.

It is separated into initial configuration for the HPS and the core configuration of the FPGA.

The initial configuration is stored in the QSPI Image and the second configuration is in the SDCard.


For a normal boot, both configurations must be of the same build.

That could be the possible problem you are facing. I could not determine that without looking at the error from the bootlog.


Regards

Jingyang, Teh


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JingyangTeh_Altera
1,103 Views

Hi


Do you have any follow up question on this?


Regards

Jingyang, Teh


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malcolm_locke
Novice
1,041 Views

Hi Jingyang,

Thanks, I think that makes some sense but I will have to re-read the information about how the configuration scheme works - it is not like the Cyclone V SoC that I am used to!

 

When you mentioned looking at the bootlog, how can I do this if I don't get anything out on the serial port?

 

Thanks

Malcolm

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SueC_Altera
Employee
1,033 Views

Malcolm -  Our architecture has changed quite a bit since Cyclone V! You may find the HPS Booting UG to be helpful.

Sue

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JingyangTeh_Altera
846 Views

Hi Malcom


In that case, if you do not get any serial output.

It is best to verify the boot binaries are generated properly or the boot related switches are toggled correctly.

If that does not work, we will need to debug it using the debugger.

Also as suggested in the previous comment, going through the boot user guide will be helpful too.


Regards

Jingyang, Teh


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JingyangTeh_Altera
766 Views

Hi


As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Regards

Jingyang, Teh


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BrianSune_Froum
New Contributor II
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@JingyangTeh_Altera 

 

I encountered the issue for 2025 and i switched to 2024.07 to confirm all basic function sanity.

Now i am switching back to settle the 2025.01 or 2025.04 issue on the boot for Cyclone V.

Same situation that after the message:

 

"

U-Boot SPL 2025.01-gcd3a9044d661-dirty (Sep 01 2025 - 08:57:07 +0800)
Trying to boot from MMC1

"

 

I had study short on that document and if not wrongly understand.

 

The A2 partition is no longer use?

The U-Boot is a must to use Jtag or QSPI or Flash based chip to store the 1st boot data?

It is possible to change to A2 partition like 2024.07?

 

Thank you

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KennyTan_Altera
Moderator
63 Views

case reopening


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BrianSune_Froum
New Contributor II
41 Views

@KennyTan_Altera 

 

Thank you for op this ticket again.

 

@JingyangTeh_Altera 

 

Under investigation we found that the das-uboot 2023 had no issue while latest 2025 not even pass the spl LD compile.

Meanwhile, the A2 settings and partition for RAW is same between u-boot-socfpga 2024 and das-uboot 2023.

With on the above info altera u-boot-socfpga 2025 aligned with the latest 2025 das u-boot.

However, only u-boot-socfpga 2025 able to compiled w/o issue but unable to load the RAW partition properlly.

 

Please help or guide what  settings are correct.

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