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305 Discussions

Warnings on files generated by Platform Designer (QSys)

MV
New Contributor I
440 Views

My (pretty much Cyclone5 SoC GHRD) project is producing almost 700 warnings. Majority of the warnings originates from files automatically generated by Platform Designer as a result of the integration of the HPS.

As an example:

 

Warning (332049): Ignored set_false_path at soc_system_hps_0_fpga_interfaces.sdc(44): Argument <from> is an empty collection
	Info (332050): set_false_path -from [get_registers {*fpga_interfaces|f2sdram~FF_3823}]
Warning (332174): Ignored filter at soc_system_hps_0_fpga_interfaces.sdc(46): *fpga_interfaces|f2sdram~FF_3831 could not be matched with a register

 

The above warning (one of many) is originated by the contents of file
\soc_system\synthesis\submodules\soc_system_hps_0_fpga_interfaces.sdc
generated by the Platform Designer with following contents (snippet):

 

...
set_false_path -from [get_registers {*fpga_interfaces|f2sdram~FF_3823}]
...

 

I can certainly comment out the contents of these .sdc files (tried successfully) but this doesn't seem right since the files are generated and perhaps the warnings have value and should be addressed properly.

Manifests without any change on Quartus Prime Lite 18.1 and 20.1

Thanks for any advice.

0 Kudos
1 Solution
KhaiChein_Y_Intel
429 Views

Hi,


This is due to the different name connected to the top level file. For example,

...

 .hps_0_hps_io_hps_io_gpio_inst_GPIO44 (hps_gpio_GPIO44),

..

In this case, you can either modify the sdc file to match the top level port name or modify the top level port name to match the name in the SDC file.


Thanks

Best regards,

KhaiY


View solution in original post

4 Replies
KhaiChein_Y_Intel
430 Views

Hi,


This is due to the different name connected to the top level file. For example,

...

 .hps_0_hps_io_hps_io_gpio_inst_GPIO44 (hps_gpio_GPIO44),

..

In this case, you can either modify the sdc file to match the top level port name or modify the top level port name to match the name in the SDC file.


Thanks

Best regards,

KhaiY


MV
New Contributor I
418 Views

@KhaiChein_Y_Intel Thank you very much.
You are right the top level names were different. These were created meaningful like the "HPS_LED" below.

.hps_0_hps_io_hps_io_gpio_inst_GPIO53 ( HPS_LED )

I was on a wrong path chasing down the port names (hps_0_hps_io_hps_io_gpio_inst_GPIO53) since these were similar to the names in the SDC file.
That was - in part - due to the fact that these names have multiple times repeated prefix "hps_io_" and that seemed to be the difference - until I figured out that it is the "HPS"LED" what counts.

Still puzzled why:
- The auto-generated SDC uses different names than desired

- Platform Designer generates port names with numerous repetitive prefixes. Tried to see how to control this and didn't find it.

Thanks!

KhaiChein_Y_Intel
415 Views

Hi,


The name is generated based on the platform designer .v file but not the project top .v file. You may need to either modify the name in the top .v file or sdc file.


Thanks

Best regards,

KhaiY


KhaiChein_Y_Intel
408 Views

Hi,


Since the workaround is provided, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY


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