Trying to follow the steps for building u-boot/bootloader from here:
https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10
It gets to a step where it calls a python script cv_bsp_generator.py, claiming it's in this directory:
$TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/arch/arm/mach-socfpga/cv_bsp_generator
But that directory doesn't exist in the repo.
Where is cv_bsp_generator.py?
連結已複製
Hi,
Which U-boot version are you using to build?
Also, have you followed all the steps properly?
The file is there:
Is it not there when after you do git checkout?
If so, could you re-try the Build U-boot steps again and let me know the results.
I'm using the version called out in my original link, which is the tutorial that all things seem to point to for SPL builds. The script is not included in that version. It is included in the version you linked. There seems to be a disconnect between that tutorial and the repo version.
It would also be nice if the scripts could be ported to python 3 (it's only been out for 15 years), or at least add details to the guide on the easiest way to run them, because simply installing python and running the scripts causes them to crash in several locations: ex, print parenthesis, unicode not defined, str =/= bytes.
I cannot get the SPL u-boot build to complete. This is the error message:
arch/arm/mach-socfpga/wrap_sdram_config.c:236:2: error: #error LPDDR2 and other DRAM types are not yet supported
Well LPDDR2 is the memory type I am dealing with for my board, and that seems to be a valid selection in the Quartus HPS configuration menu:
<parameter name="HPS_PROTOCOL" value="LPDDR2" />
and that is how the part is advertised on Intel's product webpage:
"Multiport SDRAM controller with support for DDR2, DDR3, DDR3L, and LPDDR2"
So how do I get around this issue?
Hi,
Thanks for the follow-up, that is seem to be an uncommon error that I have seen.
Can you quick share your Quartus design files? Which exact Quartus version are you using again?
I would really like to replicate this issue from my side.
Which files do you need? I am unable to give you the entire project. I was using Quartus Prime 17.0.
My general steps are:
1) Build Quartus project
2) Run bsp-editor to get the generated folder
3) git clone https://github.com/altera-opensource/u-boot-socfpga
4) run cv_bsp_generator.py
5) make socfpga_arria5_defconfig
6) make -j 48
and this is where I'm seeing the failure.
I have attached the hps_isw_handoff directory.
This is Arria 5
I'm glad it's not just me! Thank you very much for investigating, I'm interested in seeing the fix.
Hi,
Regarding the issue is due to SoC EDS is no longer required to generate the handoff folder for Cyclone V for releases 22.1std and after. Thus, there are steps different from older builds.
Thanks for you patiences, I shall let you know any new updates from our side.
Hi,
I tested using Ubuntu 18.04, also working with python 3.6, though need to do following changes:
https://bobbyhadz.com/blog/python-nameerror-name-unicode-is-not-defined
Can you re-try the build fresh, then let me know if you are still facing any issue and post the screenshot of the error.
FYI, you need to git checkout the latest Uboot version.
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Hi,
I hope that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
May I know the exact commands/steps you used to successfully build?
