delay problem

[Er7Cho1gU]

Hi there！

    I will be very grateful if someone solve my problem.  It's seem to be a basic problem, however I cound't fine a proper way to explane it.  I am very wondering why.

Program:

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module Tfine(clk_50M,clk,clkPLL,SampleClk,trig,stop,push,t,s);
input clk_50M,push;
output clk,clkPLL,SampleClk;
output reg trig,stop = 1'b0;
wire HIGH = 1'b1;
wire LOW = 1'b0;
output wire t,s;

PLL p1(.refclk(clk_50M),.rst(LOW),.outclk_0(SampleClk),.outclk_1(clk),.outclk_2(clkPLL));

assign t = (~push)&clkPLL;
assign s = t&clk;

always@(posedge t)begin
if(push == 1'b0) trig = 1'b1;
else trig = 1'b0;
end

always@(posedge s)begin
if(push == 1'b0) stop = 1'b1;
else stop = 1'b0;
end
endmodule

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Waveform on signal tap:

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My problem is I don't know why there is a delay between posedge clk and signal s.  I use a similar way to descript s and t. When clkPLL rise, t will rise immediately.  However, I cound't got a same result on t.

[RichardTanSY_Intel · Accepted solution]

Does your design meet timing?

If you simulate your design, do you see the same behavior?

Regards,

Richard Tan

[Er7Cho1gU]

I dont't familiar with timing.  Thanks forgive me a direction to fix the program！

[RichardTanSY_Intel]

You're welcome!

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[FvM]

Hello,

I presume, the design won't meet timing. The effect seen in the SignalTap recording is however of different kind. The obeserved "delay" is caused by the simple fact, that all signals are sampled by 100 MHz SampleClk. SignalTap wave form has only 10 ns time resolution. 

It's just not clear at first sight, why t edge is seen immediately and s edge one sample later. We don't know the exact PLL parameters, particularly phase relation of SampleClk, clk and clkPLL, the behaviour may be expectable by design or caused by arbitrary delay skew.

Obviously simulation will show a quite different picture, displaying signals with simulation time step.

Best regards
Frank