Intel® SoC FPGA Embedded Development Suite
Support for SoC FPGA Software Development, SoC FPGA HPS Architecture, HPS SoC Boot and Configuration, Operating Systems
461 Discussions

u-boot and FPGA to HPS SDRAM bridge, removed reset bridge in source code

PWeis4
Novice
1,378 Views

Hello,

we want to use the FPGA to HPS SDRAM bridge in our u-boot linux environment.

 

We use the altera u-boot-socfpga uboot.

Every first time the kernel hang/crashes, if we want to write trough the bridge.

After an warm reset everything works, we change nothing but boot only.

 

After a lot time of research we have found the issue.

Following function was removed from source:

u-boot-socfpga/arch/arm/mach-socfpga/misc_gen5.c

ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()

https://github.com/altera-opensource/u-boot-socfpga/commit/fce0cb41a42d46f9010b32e24c4c18e26da90a28#diff-522d7514a9bca857cf53abeb466c50e1

without this function we cant use the bridge, for the first cold boot!

 

See here

https://lists.denx.de/pipermail/u-boot/2020-February/399385.html

 

Can Altera/Intel clarify how to initialize the bridge config bits, and fix this in the source?

 

Thanks a lot

0 Kudos
7 Replies
EBERLAZARE_I_Intel
1,188 Views

Hi,

 

May I know which device you are working on? For Example in Cyclone V, we can enable the bridge via a uboot script using run bridge enable handoff in uboot.

 

I noticed you posted the same question on another post. Can we followup on one post instead?

 

Thanks.

0 Kudos
PWeis4
Novice
1,188 Views

Hello,

it is an cyclone v.

no i didnt post the same question twice times.

greetings

0 Kudos
EBERLAZARE_I_Intel
1,188 Views

Hi,

 

I apologize, were you using the latest version of Quartus and SoC EDS? For Cyclone V SoC it should be the 18.1 std.

 

May I know how did you generate your preloader and u-boot?

0 Kudos
PWeis4
Novice
1,188 Views

Hello,

yes we use the latest quartus software.

 

u-boot were from gitlab denx source, but i test although the altera source code.

same issue

but the main question is:

why is the reset removed from the source, i checked the altera source and there is the reset although removed.

with the new source code the sdram bridge is not working after power on.

plz check my links at the first post.

 

thanks

0 Kudos
EBERLAZARE_I_Intel
1,188 Views

I apologize if i missed anything, when you mentioned using altera source code, which uboot version are you working on if you may share?

0 Kudos
PWeis4
Novice
1,188 Views

Hello,

we use the uboot 2020.01 and patch the source code.

 

0 Kudos
EBERLAZARE_I_Intel
1,188 Views

Hi,

 

Thanks for the info, have you try running "run bridge_enable_handoff" in the Uboot command prompt? For Cyclone V SoC, this command need to be entered, or put in a Uboot script to enable all the bridges.

 

Also, have you tested to run our GHRD image with our guide flow to see if everything works fine using our image?:

https://rocketboards.org/foswiki/Documentation/GSRDBootLinuxSd

 

 

0 Kudos
Reply