we want to use the FPGA to HPS SDRAM bridge in our u-boot linux environment.
We use the altera u-boot-socfpga uboot.
Every first time the kernel hang/crashes, if we want to write trough the bridge.
After an warm reset everything works, we change nothing but boot only.
After a lot time of research we have found the issue.
Following function was removed from source:
ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
without this function we cant use the bridge, for the first cold boot!
Can Altera/Intel clarify how to initialize the bridge config bits, and fix this in the source?
Thanks a lot
May I know which device you are working on? For Example in Cyclone V, we can enable the bridge via a uboot script using run bridge enable handoff in uboot.
I noticed you posted the same question on another post. Can we followup on one post instead?
I apologize, were you using the latest version of Quartus and SoC EDS? For Cyclone V SoC it should be the 18.1 std.
May I know how did you generate your preloader and u-boot?
yes we use the latest quartus software.
u-boot were from gitlab denx source, but i test although the altera source code.
but the main question is:
why is the reset removed from the source, i checked the altera source and there is the reset although removed.
with the new source code the sdram bridge is not working after power on.
plz check my links at the first post.
Thanks for the info, have you try running "run bridge_enable_handoff" in the Uboot command prompt? For Cyclone V SoC, this command need to be entered, or put in a Uboot script to enable all the bridges.
Also, have you tested to run our GHRD image with our guide flow to see if everything works fine using our image?: