Acquire Performance Counters from within an Enclave

[giovanni_m_1]

Hello to Everybody,

I would like to get access to the CPU performance counters from within an Enclave. Initially I wanted to access directly from inside. So at the beginning I tried to execute an assembly code able to access a general register and everything seemed perfect. However, after a while I realized that the PCM registers can be accessed only on ring0 which is not the enclave case since it runs in ring3. Doh!! So now what to do? What is the most secure way?

I have no other choice than leveraging the Intel's PCM APIs outside of the enclave and pass the data into it?

Thank you in advance

[Francisco_C_Intel]

Does VTune provide what you need? On Windows, SGX PSW 1.6 has support for VTune.

If you are doing this by hand, are you in Windows or Linux? At a high level, you need to launch the enclave in DEBUG=1 mode, and then for every TCS, you need to set the debug opt-in bit to 1. If you don't do this, the performance counter registers don't work.

See

https://software.intel.com/en-us/forums/intel-software-guard-extensions-intel-sgx/topic/657458

[giovanni_m_1]

Well,

Thank you very much for the response. That was my backup solution. At the end I discovered that modifying a CPU flag into CR4 you can be able to enable the usage of RDPCM at ring3 level. In this way I can be able to enforce the ASM code from within the enclave. 

Thanks,

Regards