Kaseyville (Granite Rapids-D) : Question regarding DDR5 1-DPC design and tabbed routing

[jungsoolim]

We are planning to design a DDR5 system with a 1-DPC (one DIMM per channel) configuration, referencing the Kaseyville CRB for the layout design. Is tabbed routing essential for this design? Unfortunately, we do not have access to the Cadence high-speed tool, which means we cannot apply tabbed routing.

As an alternative, we are considering implementing 1-DPC in our design instead of 2-DPC. Could you please clarify if this approach will meet the design requirements for DDR5?

[Dineshbabu · Accepted solution]

Hi jungsoolim,

Greetings!

Thank you for posting in the Intel Community. Your query is related to designing a DDR5 system on Kaseyville (Granite Rapids - D). We recommend creating a ticket with the Intel® Software Development Platform (Intel® SDP).

Please refer to the article below to create a support ticket in Intel SDP:

https://www.intel.com/content/www/us/en/support/articles/000095889/programs.html

Since we have referred you to Intel SDP, we will be closing this request. If you have any further questions in the future, please don’t hesitate to reach out. Feel free to start a new conversation, as this thread will no longer be monitored.

Regards,

Dinesh

Intel Customer Support Technician