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I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 500 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 500 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
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Hello Sumanth,
Greetings from Intel!
Thank you for contacting Intel. To proceed further with your query, I kindly request that you share the below details:
1. Product detail
2. Elaborate the issue that you are facing.
Regards,
Amina
Intel Customer Support Technician
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I am using a 10CX150YF672E5G Cyclone 10 GX FPGA with the Remote Update IP version 19.1.0. Soon after reset, writing to the update register and triggering reconfiguration did not work. However, if I waited for around 300 µs after resetting the Remote Update IP, the subsequent write to the update register and reconfiguration trigger worked as expected.
Is there any required initialization time for the Remote Update IP after reset?
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Hello Sumanth,
Greetings!
For this, we would recommend you kindly post your query in the FPGA community forums and the concerned team will get in touch with you and assist you further.
Do note that FPGA community forums and blogs have moved to the Altera Community. Existing Intel Community members can sign in with their current credentials.
Hence, this thread shall no longer be monitored.
Thank you for using Intel products and services.
Best Regards,
Azhari_Intel
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