Does This FPGA Matmul Example Use Systolic Array?

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Does This FPGA Matmul Example Use Systolic Array?

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Hello,

I am pretty new to oneAPI and HLS, so I wanted to confirm my analysis of one of the reference design codes from Intel oneAPI-samples Github.

I was looking for a systolic-array-based matrix multiplication using oneAPI and found this reference design:
https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/ReferenceDesigns/matmul

It said in the readme file that it demonstrates a systolic-array-based high-performance general matrix multiplication on an FPGA. But as I was going through the memory transfer and computation code, it seemed like it was not implementing systolic-array-based computing. I could not see any data transfer from one processing element to another.

Am I missing some part or is it not using systolic-array-based matrix multiplication?

Thanks,

Junsang Yoo

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