Can I control/limit CPU mask for tbb tasks by this way?

[Li_Feng]

Hello,

I have socket comminication and image decoding tasks who need binding CPUs to process in time, and tbb tasks to process images parallelly and immediately.

Socket comminication and image decoding tasks work well separately without tbb tasks. So far as I know, tbb will try to use all available CPUs. So I want to control CPUs for tbb tasks as below:

(1) socket tasks: CPUs 4,5,6,7

(2) image decoding tasks: CPUs 8,9,10,11

(3) tbb tasks: CPUs 12~63

Can I realize my aim like this at programm initialization:

------------------------------------------------------------------------------------------

SetProcessAffinityMask(GetCurrentProcess(),0xFFFFFFFFFFFFF000);

task_scheduler_init init;

SetProcessAffinityMask(GetCurrentProcess(),0xFFFFFFFFFFFFFFF0);

------------------------------------------------------------------------------------------

Thanks a lot!

[SeshaP_Intel]

Hi,

Thank you for posting in Intel Communities.

Could you please try with the latest oneAPI Threading Building Blocks (oneTBB)?

In your case, you can try the task_arena::constraints structure to prefer the NUMA node or preferred core type for running TBB tasks on selected CPU cores.

You can create a separate task_arena for different NUMA nodes to run the tasks on different CPU cores.

Please refer to the below links for more information.

https://oneapi-src.github.io/oneTBB/main/tbb_userguide/Migration_Guide.html

https://oneapi-src.github.io/oneTBB/main/tbb_userguide/Guiding_Task_Scheduler_Execution.html

Please let us know if you face any issues.

Thanks and Regards,

Pendyala Sesha Srinivas

[SeshaP_Intel]

Hi,

Has the information provided above helped? If yes, could you please confirm whether we can close this thread from our end?

Thanks and Regards,

Pendyala Sesha Srinivas

[SeshaP_Intel]

Hi,

Since we didn't hear back from you, we assume that your issue is resolved. If you need any additional information, please post a new question as this thread will no longer be monitored by Intel.

Thanks and Regards,

Pendyala Sesha Srinivas