DE1_SOC THDB-ADA waveform(Signal tap logic analyzer)

[DE1SOCman]

Hello, I am working on a project to control THDB-ADA (high speed) through the DE1_SOC board to output triangular and sawtooth waves in the DAC channel.

I wrote the code and succeeded in compiling it, and the output equipment I have now checks the output through the oscilloscope. To get the output, I used CLOCK_50 inside the board and set up the node. However, the waveform I can see is the waveform as shown in the picture below, and the desired waveform does not appear.

Is there a solution? I attach a code and a picture

Thank you.

module DE1_SOC(
// 기타 포트들 그대로 두고

// DAC 관련 포트
output [13:0] DAC_DA, // 14-bit Triangle wave for DAC_A
output [13:0] DAC_DB, // 14-bit Sawtooth wave for DAC_B
output DAC_CLK_A, // Clock for DAC_A
output DAC_CLK_B, // Clock for DAC_B
output DAC_MODE, // DAC mode (normal)
output DAC_WRT_A, // Write signal for DAC_A
output DAC_WRT_B, // Write signal for DAC_B

// CLOCK_50 입력 추가
input CLOCK_50 // 50 MHz clock input
);

//=======================================================
// REG/WIRE declarations
//=======================================================
reg [13:0] triangle_wave_A; // 14-bit triangle wave
reg [13:0] sawtooth_wave_B; // 14-bit sawtooth wave
reg [15:0] counter_triangle; // 16-bit counter for triangle wave
reg [15:0] counter_sawtooth; // 16-bit counter for sawtooth wave

// 추가된 DAC 쓰기 신호 제어
reg DAC_WRT_A_reg;
reg DAC_WRT_B_reg;
reg [15:0] write_counter_A; // Write signal timing for DAC_A
reg [15:0] write_counter_B; // Write signal timing for DAC_B

//=======================================================
// Triangle Wave Generation for DAC_A
//=======================================================
always @(posedge CLOCK_50) begin
if (counter_triangle < 16'd16383) begin
counter_triangle <= counter_triangle + 1;
triangle_wave_A <= counter_triangle[13:0]; // 14-bit increasing triangle wave
end else if (counter_triangle < 16'd32767) begin
counter_triangle <= counter_triangle + 1;
triangle_wave_A <= 16'd32767 - counter_triangle[13:0]; // 14-bit decreasing triangle wave
end else begin
counter_triangle <= 0; // Reset counter when full cycle is done
end
end

//=======================================================
// Sawtooth Wave Generation for DAC_B
//=======================================================
always @(posedge CLOCK_50) begin
if (counter_sawtooth < 16'd16383) begin
counter_sawtooth <= counter_sawtooth + 1;
sawtooth_wave_B <= counter_sawtooth[13:0]; // 14-bit increasing sawtooth wave
end else begin
counter_sawtooth <= 0; // Reset counter when full cycle is done
end
end

//=======================================================
// DAC Write Signal Generation for DAC_A and DAC_B
//=======================================================
always @(posedge CLOCK_50) begin
// 1ms 간격으로 DAC 쓰기 신호를 토글 (주기적으로 기록하도록)
if (write_counter_A == 16'd50000) begin
DAC_WRT_A_reg <= ~DAC_WRT_A_reg;
write_counter_A <= 0;
end else begin
write_counter_A <= write_counter_A + 1;
end

if (write_counter_B == 16'd50000) begin
DAC_WRT_B_reg <= ~DAC_WRT_B_reg;
write_counter_B <= 0;
end else begin
write_counter_B <= write_counter_B + 1;
end
end

//=======================================================
// Assignments for DAC Outputs
//=======================================================
assign DAC_DA = triangle_wave_A; // 14-bit Triangle wave for DAC_A
assign DAC_DB = sawtooth_wave_B; // 14-bit Sawtooth wave for DAC_B

assign DAC_CLK_A = CLOCK_50; // Clock for DAC_A
assign DAC_CLK_B = CLOCK_50; // Clock for DAC_B
assign DAC_MODE = 1'b0; // Normal DAC mode (not in test mode)
assign DAC_WRT_A = DAC_WRT_A_reg; // Write signal for DAC_A
assign DAC_WRT_B = DAC_WRT_B_reg; // Write signal for DAC_B

endmodule