Clock in Backplane Ethernet 10GBASE-KR PHY

Items with no label

Clock in Backplane Ethernet 10GBASE-KR PHY

220 Views

Hello.

I have been trying unsuccessfully for several days to run 10G with Link-Training and FEC in Arria V GZ.

Why 10GBASE-KR PHY have such a useless description?

It is completely unclear how it should be clocking. I can not find a example of a project with this megafunction in wiki.

I don’t understand how to clock the ports xgmi_tx_clock and xgmi_rx_clock. Why both clk are input?

I tried to generate 156.25 Mhz with PLL from ref_clk and apply to these ports, but I got a slacks between the frequencies of the PLL and clk33pcs. Please, send me any project with this megafunction so that I have at least some idea of how to connect it.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.