DE0-CV Board - Clock Manager IP module for 200 MHz frequency

[anm]

Hi,

this is my first interaction with Intel FPGAs and Intel's Forum. :)

I have a DE0-CV Board with a Cyclone V on it (CycloneV 5CEBA4F23C7N ).

The Board has 4x50 Mhz Buffered Clocks.

I want to generate a frequency of 200MHz for my design.

 Is there an IP module (like a Digital Clock Manager) provided, that will do this conversion and output a clock signal of 200 MHz for my design?

Is there documentation containing such IP modules (Clock Managers, Clock Buffers, etc.) for Cyclone V FPGAs?

I am using Quartus Pro v19.4.

Thank you in advance for your response and time.

Kind regards,

anm

[anm]

Update:

I found this IP at the Documentation Center:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf

Is this the right IP core to use, in order to create the 200MHz frequency?

The board also has 4 Fractional PLLs. Will the Quartus use the above IP and implement it on one of the Fractional PLLs in order to create the 20MHz clock frequency?

Kind regards,

anm

[anm]

UP

Is anyone monitoring these discussions?