I need to add two 1-bit(std_logic) unsigned numbers and need to store in a 2 bit(std_logic_vector) vector in VHDL. Is it possible to do so. If so, then please help me to do so. Thanks in advance here is my,code

[svenk19]

ibrary ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity FullAdd is port ( 

A, B, Cin: in std_logic;

Sum, Cout: out std_logic 

); 

end FullAdd;

architecture behavioral of FullAdd is

signal ans:std_logic_vector(1 downto 0) := "00";

begin

process(a,b,cin)

begin

ans <= "0"&a+b+cin;

sum <= ans(0);

cout <= ans(1);

end process;

end behavioral;