Hi,
I was trying to understand a PCI hierarchy with lspci when some questions came to me.
I had never really thought of it, but PCI bridges still have one configuration space, right? and only one device:bus:function address, right?
So my first question would be, which side of the bridge does that information refer to? the upstream or the downstream?
Also in the same line, but moving more to PCIe specifically, what side of the bridge is the information in the PCIe capabilitiy structure refering to? I mean we have a Link Capabilities for example, which tells us how fast that port can go, but what side is that info refering to?
I suspect I am thinking about this wrong but I can't see how, could someone enlighten me?
Thanks!
-Albert.
