hello, I am new in fpga, I want simulate a 4-bit adder. below is the vhdl code. Quartus has successfully complied the code but when i try to simulate it with the "Univesity Program vwf" , I get this error
Error: Sub-system: WSC, File: /quartus/neto/wsc/wsc_port.cpp, Line: 409 m_port_info.num_of_dimensions() == 1
The vhdl code
library ieee;
use ieee.std_logic_1164.all;
entity adder3 is
port (
a_string, b_string : in integer range 0 to 15;
cin : in integer range 0 to 1;
sum_string : out integer range 0 to 31
);
end adder3;
architecture arc of adder3 is
begin
sum_string <= a_string + b_string + cin;
end arc;
Regards
