lfsr code for bit swapping between bits if lsb is 0 in verilog in a 8 bit code

SSRIV16 · ‎02-22-2020

I tried writing the code but desired ouput is not generated ,please help me out as early as possible,i need to submit my assignment before 25 feb. lfsr code to swapping bits B7 and B6 when lsb i.e B0 is O here in this generated code output coming is wrong ,please help me out as early as possible designed various block as well as connection ,earlier the error was regarding output and inout ports but i resolved that

 module R_DFF(
    input clk,
    input d,
     output q
    );
     wire g2,r,s,g1;
     reg b;
    initial b= 1'b1; 
     PG d2(clk,b,1'b0,d,g1,q,r,g2);
     always@(*)
      begin
      b = r;
      end
endmodule
 
module PG(
    input a,
    input b,
    input c,
    input d,
    output reg p,
    output reg q,
    output reg r,
    output reg s
    );
 
always@(*)
begin
 p = a;
 q = (((~a)*b)^(a*d));
 r = (((~a)*b)^(a*d)^c);
 s = (b^d);
end
endmodule
 
 
 
 
 
module DFG(
    input a,
    input b,
    input c,
    output reg p,
    output reg q,
    output reg r
    );
     initial
     assign p=a;
     initial
     assign q=a^b;
     initial
     assign r= a^c;
endmodule
 
 
 
module FG(
    input a,
    input b,
    output reg p,
    output reg q
    );
     initial
     begin
      p = a;
       q = a^b;
      end
endmodule
 
 
 
module R_bs_lfsr8(
input reg clk,
output wire [0:7]q,
output reg [0:7]OUT
    );
 
reg d;
reg sel;
 
 
wire [0:7]q1;
wire [0:7]g1;
wire [0:2]g2;
wire [0:2]x1;
wire [0:2]x2;
initial d=1'b1;
assign g1=8'b10000001; 
R_DFF f1(clk,d,q1[0]);
FG m1(q1[0],1'b0,q[0],g1[0]);
 
R_DFF f2(clk,g1[0],q1[1]);
FG m2(q1[1],1'b0,q[1],g1[1]);
 
R_DFF f3(clk,g1[1],q1[2]);
FG m3(q1[2],1'b0,q[2],g1[2]);
 
R_DFF f4(clk,g1[2],q1[3]);
DFG m4(q1[3],1'b0,1'b0,q[3],g1[3],g2[0]);
 
R_DFF f5(clk,g1[3],q1[4]);
DFG m5(q1[4],1'b0,1'b0,q[4],g1[4],g2[1]);
 
R_DFF f6(clk,g1[4],q1[5]);
DFG m6(q1[5],1'b0,1'b0,q[5],g1[5],g2[2]);
 
R_DFF f7(clk,g1[5],q1[6]);
FG m7(q1[6],1'b0,q[6],g1[6]);
 
R_DFF f8(clk,g1[6],q1[7]);
FG m8(q1[7],1'b0,q[7],g1[7]);
 
 
FG m9(g1[7],g2[2],x1[0],x2[0]);
FG m10(x2[0],g2[1],x1[1],x2[1]);
FG m11(x2[1],g2[0],x1[2],x2[2]);
        assign g1 = q;
always@(negedge clk)
      begin
      d <= x2[2];
      sel= q[7];
 
 
begin 
if(sel == 1'b0)
    begin
         OUT[0]<= q[1];
         OUT[1]<= q[0];
         OUT[2]<= q[3];
         OUT[3]<= q[2];
         OUT[4]<= q[5];
         OUT[5]<= q[4];
         OUT[6]<= q[6];
         OUT[7]<= q[7];
    end
else if(sel == 1'b1)
    begin
         OUT[0]<= q[0];
         OUT[1]<= q[1];
         OUT[2]<= q[2];
         OUT[3]<= q[3];
         OUT[4]<= q[4];
         OUT[5]<= q[5];
         OUT[6]<= q[6];
         OUT[7]<= q[7];
    end
 
end
      end
 
 
 
endmodule
 
 
 
 
 
 
module R_bs_lfsr8_tb;
 
 reg clk;
wire [0:7]q;
wire [0:7]out;
 
 
R_bs_lfsr8 lf(clk,q,out);
initial
begin 
 
    clk=0;
    forever #10 clk=~clk;
end
initial 
begin
    force   lf.q=8'b10000001;
            #91;
    release lf.q;
end
endmodule