In 2014 a bug was found in the Haswell TSX implementation, documented here:
http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200v3-spec-update.html Intel® Xeon® Processor E3-1200 v3 Family: Specification Update
(HSW136).
Are there any intel chips currently on the market that have a fix for this issue? How would such a chip be identified on the command line on Linux (RHEL7).
Prior to the errata publication for this issue, I believe we could look for RTM programmatically with code like:
# if defined USE_LIBCPUID
# include
# endif
# include
constexpr int RTM_BITMASK (1 << 11) ;</span>
int main()
{
# if defined USE_LIBCPUID
struct cpu_raw_data_t raw ;
if ( cpuid_get_raw_data( &raw ) >= 0 )
{
printf( "%08X\n", raw.basic_cpuid[7][1] & RTM_BITMASK ) ;
}
# endif
int r[4] { 7, 0, 0, 0 } ;
__asm__( "cpuid"
: "+a"( r[0] ),
"=b"( r[1] ),
"+c"( r[2] ),
"=d"( r[3] ) ) ;
printf( "%08X\n", r[1] & RTM_BITMASK ) ;
return 0 ;
}
Given that this will also be true for chips that have the bug but do not have the microcode update that disables it (nor a bios update for the same), how would one check that the TSX feature is both available and bug free?
連結已複製
If your CPU has this bug, and if it can be fixed by a microcode update, you can load the respective microcode file (available https://downloadcenter.intel.com/de/download/24661/Linux-Prozessor-Mikrocode-Datendatei here) at boot time provided you've the respective feature compiled into your kernel.
If it can't be fixed by a microcode update, your only other option is a BIOS update that has to be provided by your board's manufacturer.
I have a fairly recent Intel NUC6i5SYH machine with cpu type:
Intel(R) Core(TM) i5-6260U CPU @ 1.80GHz
From what I gather this cpu is 6th generation (skylake), and shouldn't have this issue, since only haswell (4th) and some broadwell (5th) generation cpus had the TSX bug. Despite that /proc/cpuinfo shows no rtm nor no hle flags:
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch epb intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid mpx rdseed adx smap clflushopt xsaveopt xsavec xgetbv1 dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp
This is also confirmed running cpuid ( http://www.etallen.com/cpuid/cpuid-20151017.src.tar.gz http://www.etallen.com/cpuid/cpuid-20151017.src.tar.gz ) which shows:
cpuid-20151017> ./cpuid | grep -ie rtm -e hle
HLE hardware lock elision = false
RTM: restricted transactional memory = false
HLE hardware lock elision = false
RTM: restricted transactional memory = false
HLE hardware lock elision = false
RTM: restricted transactional memory = false
HLE hardware lock elision = false
RTM: restricted transactional memory = false
The (Intel Visual) BIOS has no options that I can find to disable TSX (or re-enable it if disabled).
Hi Amy,
If it makes it any easier, you can ignore my original question, and just answer the question from my "May 11, 2016 10:06 AM" post. Why is it that I don't appear to have RTM/HLE available on a Intel NUC6i5SYH system that is running a hardware version (skylake) that is supposed to have the fix for the original Haswell issue. Can TSX be enabled on such a system? How?
Peeter
Hi,
I am probably confused and may need that you help me understand your question.
Intel® TXT is part of Intel® vPro™ Technologies and if no vPro then no TXT. The NUC6i5SYH is not Vpro enabled. See for example NUC5i5MYBE TPS: http://www.intel.com/content/dam/support/us/en/documents/boardsandkits/NUC5i5MYBE_TechProdSpec06.pdf http://www.intel.com/content/dam/support/us/en/documents/boardsandkits/NUC5i5MYBE_TechProdSpec06.pdf page # 14
Let me know if this helps,
Ronny G
Hi Ronny,
Assuming that you mean TSX when you write TXT, this seems to answer the question. After seeing the processor spec sheet in the URL you mentioned, I looked up the same for the CPU in my NUC:
http://ark.intel.com/products/91160/Intel-Core-i5-6260U-Processor-4M-Cache-up-to-2_90-GHz http://ark.intel.com/products/91160/Intel-Core-i5-6260U-Processor-4M-Cache-up-to-2_90-GHz
and see, sure enough, that TSX is not enabled.
Is this feature always going to be tied to the vPro line of CPUs for future chips? I didn't read of any such restriction in the Haswell release when it was first introduced (at least until the bug was found).
Peeter
