Intel Quartus Qsys

[Subhabrata]

I have created NIOS II based system in Qsys (Quartus Prime Lite 18.1). completed all connection, memory mapping and IRQ. 

But to generate HDL (Generate -> generate HDL), I am getting only .v and .sv file as output, though I have selected VHDL as HDL source. 

[Jocelyn_Intel]

Hello, @Subhabrata  

Thank you for posting on the Intel® communities.  

For any issues, inquiries, documentation or license, please go to the Intel Community - FPGAs and Programmable Solutions and post your question on the appropriate subforum topic.   

This thread will no longer be monitored. Thank you for your understanding. 

Best regards,  

Jocelyn M.   

Intel Customer Support Technician.