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Interrupts during read /write cycles

idata
Employee
‎01-26-2011 02:42 PM
1,530 Views

Hi, I have a question which i know the answer for older CPUs but not for I7 and i couldn't find any document which could answer these questions.

Basically how does the CPU ensure data intergity if hardware interrupts occure in the middle of read/write data operations.

From memory for older CPUs. This is how it used to work.

If the opcode involves a single byte then opcode is completed before interrupt is handled

On opcodes involving writing/reading to 2 byte (or more) the interrupt is handled differently.

Can anyone please fill the gap? Thank you.

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