MEM_BOUND_STALLS.IFETCH_L2_HIT

[Shiju]

what does the counter MEM_BOUND_STALLS.IFETCH_L2_HIT represent? I am confused with the wording given "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache." 
Does this mean that , "there was an L1 cache miss and core was stalled" OR " cpre stalled because there was a miss to hit L2 cache" ??

Any views ?

[그래요ITech]

Hi Shiju

The counter MEM_BOUND_STALLS.IFETCH_L2_HIT represents the number of cycles during which the CPU core is stalled because it's waiting for instructions that were not found in the L1 cache (instruction cache or TLB miss) but were subsequently found in the L2 cache. So, this counter increments when there's an L1 cache miss that results in a hit in the L2 cache, causing the core to stall while it retrieves the instructions. It does not mean that the core is stalled due to a miss in the L2 cache; rather, it's stalled because it's waiting for data that had to be fetched from the L2 cache due to a miss in the L1 cache.

Cheers,

Max