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Hi,
I have a brand new system with a MSI Meg Ace Z890 motherboard and the Intel 285k.
I have a 4TB Samsung 9100 Pro NVME drive installed in the Gen5 x4 M.2_1 slot which is directly connected to the CPU PCIe lanes (see attached block diagram).
The 9100 pro is capable of upwards of 14BGB/sec throughput but I'm only seeing 12GB/sec.
I've read the articles about the gen 5 NVME drives being throttled due to the Arrow Lake chiplet design, but I'm assuming this would impact drives connected via the PCH. My drive is directly connected to the CPU (Arrow Lake has 20 gen 5 PCIe lanes, I'm using 16 for the GPU and 4 for the 9100 pro).
Please can you help me with the following questions:
1. Why am I being throttled in the above scenario?
2. What is the fix?
Thanks.
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Hi Hamster_97,
Thank you for reaching out to the Intel Community Forum.
The upstream memory read performance of the ARL S processor SOC tile root ports 13 and 14 (PCIe Lanes 1 to 16), configured as 1px16 or 2px8, may be reduced due to increased roundtrip latencies during random upstream memory read operations. These latency variations depend on the specific workload and the capabilities of the PCIe endpoint device.
Results could be caused by the system configuration and/or SoC architecture.
If you have any questions, please let us know. Thank you.
Best regards,
Archie D.
Intel Customer Support Technician
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Thank you for your reply but I'm not very happy with this answer. The CPU is advertised as having 20 gen 5 PCIe lanes. If I'm using 4 of those for my M.2 SSD, this should allow 16 GB/s throughput, except it doesn't. It provides 12 GB/s, which is false advertising.
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2. There really is no solution AFAIK. The PCIe lanes in the PCH are only Gen4, so they don't represent an alternative.
Just saying,
...S
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I am speculating somewhat here, not 100% sure -- If you have a super smart (read: expensive) M.2 PCIe board that handles the per-SSD bifurcation itself (perhaps to also support RAID?), you would be asking the processor to bifurcate from x16 to x8x8, which is universally supported. With a dumb (read: less expensive) M.2 PCIe board, on the other hand, you would be asking for the processor to bifurcate from x16 to x8x4x4. The 285K can handle this ask (they document this as '1x8+4x4'; they included the Gen4 x4 lanes also offered by this processor), but not necessarily every motherboard. There is a lot of fragmentation in the bifurcation options supported by the BIOSs of the various motherboard vendors.
Just a buyer-beware,
...S
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Hi Hamster_97,
I will check this in my end and will get back to you once a resolution is available. Thank you for your patience and understanding.
Best regards,
Archie D.
Intel Customer Support Technician
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Hi Hamster_97,
I have conducted a thorough investigation and identified other cases with similar inquiries.
My findings indicate that the upstream memory read performance of the ARL S processor SOC tile root ports 13 and 14 (PCIe Lanes 1 to 16), configured as 1px16 or 2px8, may be affected by increased round-trip latencies during random upstream memory read operations. These latency variations are influenced by the specific workload and the capabilities of the PCIe endpoint device.
As a result, the observed performance could be attributed to the system configuration and/or SoC architecture. Given the nature of this issue, I recommend contacting the motherboard OEM for further assistance and guidance.
Since this is the case, I will be closing this inquiry. If you need further assistance, please submit a new question, as this thread will no longer be monitored.
Best regards,
Archie D.
Intel Customer Support Technician

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