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Xeon D 1559

Jinto
Novice
‎07-28-2020 01:21 PM
1,232 Views

Xeon D spec says maximum 32 lanes of PCIe is possible. Does it mean any lanes are multiplexed with SATA or any other interfaces? Do we need to compromise on any other interface to utilise all 32 lanes of PCIe?

Where can we find relevant documentation? Please review feasibility of PCIe lane allocation in attached document

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Emeth_O_Intel
Moderator
‎07-28-2020 05:49 PM
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Hello,


Thank you for contacting Intel Xeon Community Support.


Please create your question in the following forum of Intel Embedded Server:


https://community.intel.com/t5/Embedded-Server/bd-p/emb-server-hardware-software-firmware


They will be more than happy to assist you and provide you the most accurate information.


Regards,


Emeth O.

Intel Server Specialist.





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