If I am using cyclone V GT fpga , can I expect to get 128bits data per clock cycle from avalon interface at 200 MHz?
If not what is the max data width and frequency of memory controller(avalon ) a good code can achieve ?
The width of data bus on the Avalon-MM interface is depend on the particular protocol's data width.
Full rate results in a width of 2× the memory data width. Half rate results in a width of 4× the memory data width. Quarter rate results in a width of 8× the memory data width. To determine the Avalon-MM interface rate selection for the memory, refer to the local interface clock rate for your target device in the External Memory Interface Spec Estimator here --> https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/exter...