Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12435 Discussions

PCIe DMA not working for addresses above 4GB

Honored Contributor II


I am implementing a KMDF driver for Altera Stratix4 PCIe board on Windows7 64 bit PC ( Both OS and processor are 64 bit). The devices needs that I create a Descriptor Table(DT) in a non paged memory that contains the Phy address and length of each page of the DMA buffer. Then the base physical address of this Descriptor Table is written to a device register and the device starts DMA.  



I see that dma works only when phy address of both buffer and the DT are below 4GB( ie.. Highpart of the phy address is 0) . When either one of these address are above 4GB the device registers indicate that data is transferred but the data does not arrive to PC (in case of Dev to Host).  



The device manual says that it is capable of 64 bit addressing. So do i need to do anything in the driver or host side to make the 64 bit addresses work? 



Thanks in advance.
0 Kudos
2 Replies
Honored Contributor II

A master in SOPC Builder or Qsys can only access up to 4GB. This is due to the address width in the Avalon spec only supporting up to 32 bits.

Honored Contributor II

You need to use the streaming interface for 64bit transfers.