A_en is 'X' problems

[Altera_Forum]

Hi there, 

i have wrote some VHDL program in QuartusII (10.1)as custom instruction for NIOSII and implemented a SOPC system with Nios II. Then i go to the EDA (eclipse) generate a hallo world program and run it in Modelsim(6.4b). And everything is ok untill this error pop up in modelsim: # 314830 ns: ERROR: NIOS_test_bench/A_en is 'x'# ** Failure: VHDL STOP# Time: 314830 ns Iteration: 1 Process: /test_bench/dut/the_nios/the_nios_test_bench/#MERGED#line__877,842,786,768,731,713,695,677,641,623,605,587,531,494 File: /home/Desktop/dct_transform/NIOS_test_bench.vhd# Break in Architecture europa at /home/Desktop/dct_transform/NIOS_test_bench.vhd line 598  and the relative Code is generated automatically by SOPC builder :   process (clk)  VARIABLE write_line5 : line;  begin  if clk'event and clk = '1' then  if std_logic'(reset_n) = '1' then   if is_x(std_ulogic(A_en)) then   write(write_line5, now);  write(write_line5, string'(": "));  write(write_line5, string'("ERROR: NIOS_test_bench/A_en is 'x'"));  write(output, write_line5.all & CR);  deallocate (write_line5);  assert false report "VHDL STOP" severity failure;  end if;  end if;  end if;  end process;  ok, please help!!!:(

[Altera_Forum]

'X' usually occurs when you drive one signal from multiple places. You'll have to look at the drivers of A_en.

[Altera_Forum]

This typically happens when unknown instructions (due to uninitialized memory) are fetched by the master. Make sure your code RAM is being properly initialized for the simulation flow. 

 I recommend reading though this document to make sure you are not missing a step: http://www.altera.com/literature/an/an351.pdf

[Altera_Forum]

--- Quote Start ---  'X' usually occurs when you drive one signal from multiple places. You'll have to look at the drivers of A_en.  --- Quote End ---    thx for reply, but what is A_en, i didn't define this signal...:(

[Altera_Forum]

--- Quote Start ---    thx, i'll read it through.:)

[Altera_Forum]

It's a pipeline enable for the 'Align' stage of the processor pipeline. The processor simulation files are coded to catch cases where unknown values trickle through the pipeline.

[Altera_Forum]

Hi there, 

i go through that procedure in the handbook, and i have found the mem initial file(including hex and dat files). but it still doesn't work.

[Altera_Forum]

ok, problems are resolved, thx guys

[Altera_Forum]

Hello 

 I have the same problem , can you explain what you did to fix it please.   Regards   Ben

[Altera_Forum]

Hi, Ben  

Unfortunately, i didn't really "solve" that problem. I don't know what i may messed up something during the project. i just delete the whole project except the source code which i 've wrote, and regenerate it from the very beginning, and the error is gone. i don't know, maybe you should try this, but before you delete anything, i suggest you check your development process according to the Altera Handbook carefully.  i hope that can help you.  best regards

[Altera_Forum]

Cured by setting up reset and clk signals correctly before simulating. I left them in the default state and they need forcing.. 

 for example  force reset 1, 0 40 force clk 1, 0 10 -repeat 20  This is true for Qsys simulations at least.

[Altera_Forum]

Forcing is a little extreme here. It is usualy best just to initialise the signals properly in the testbench.

[Altera_Forum]

It works for me. Basically there is no clock or reset assertion unless I set them up myself.  

 How do you initialise them in the testbench?

[Altera_Forum]

For VHDL, you give them an Initial value: 

 signal clk : std_logic := '0';

[Altera_Forum]

Oh... that's not what I meant. :)  

 I need to set the the clock toggling high and low and set the reset high to start with and then set it low.... Otherwise I get the A_en is 'X' problem.   I didn't have this issue with SOPC.... I could run my simulations after entering the 's' macro into modelsim.... For some reason I have to setup my clocks and reset while simulating from Qsys...

[Altera_Forum]

Okay I found the real problem and it was down to me. For some reason I had the jtag_debug_module_reset connected to the other reset lines. As soon as I disconnected this it ran correctly from the BFM.  

 Now I have the Clock Source driving the clk and clk_reset to the rest of the system and the error is gone.

[Altera_Forum]

This sounds like a bug to me if I understood your connectivity. You should be able to connect the JTAG debug module reset request to the Nios II processor. If you have the simulation up can you check what state that reset request is in, I'm suspecting it's driven to 'X' and causing this problem.

[Altera_Forum]

I had the JTAG debug module reset connected to all components' reset. I will check when I have a sec to do so....