A problem about running in Nios IDE

[Altera_Forum]

Hi, everyone, I met a strange problem. 

 After I complied the project(standard project, I added user logic and assign pins) in Quartus II 5.0 successfully, and download the .sof file into the Altera dev board, Stratix edition, when I want to run a simple project in NIOS II IDE 5.0 with a hello world template, then a problem occurs in IDE console.  >>Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 >>Pausing target processor: not responding. >>Resetting and trying again: FAILED >>Leaving target processor paused  I search this problem in google and other search engines. FAE in altera had explained this problem before, with two possible reasons. One is accidental error between Nios II CPU and IDE software through USB-Blaster, and you could resolve this problem with downloading the sof file and run again. The other was making the tools consistency(Nios II IDE 6.0, Quartus II 6.0), rebuilding the system again.  I followed the instruction, but can not get the right result!  And some guys say it is related with clock and time sequence of sdram, but does not gives the solutions.  3xs for help!

[Altera_Forum]

You can use the Altera development kits setting include the DRAM timing setting. 

Or you can adjust the DRAM clock step by step until it is ok.

[Altera_Forum]

>>You can use the Altera development kits setting include the DRAM timing setting. 

 I've already use the default setting in Aletra dev kits.

[Altera_Forum]

Hi, hugo_liu, 

 >>Or you can adjust the DRAM clock step by step until it is ok.  I am not quite sure about the dram clock modification. You mean I should do like this, changing the sdram timing parameter in sdram controller component provided by SOPC Builder, such as CAS latency cycles, access time...

[Altera_Forum]

--- Quote Start ---  originally posted by bluebell_ll@Jan 25 2007, 09:21 PM hi, hugo_liu,  >>or you can adjust the dram clock step by step until it is ok.  i am not quite sure about the dram clock modification. you mean i should do like this, changing the sdram timing parameter in sdram controller component provided by sopc builder, such as cas latency cycles, access time... <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20864)  --- quote end ---    --- Quote End ---    I suggest that firstly, you only use the standard project to try it. Then you can add your design. If there are some problem in the standard project then you will check your hardware board.  To adjust the dram clock is that to adjust your clock phase.

[Altera_Forum]

--- Quote Start ---  originally posted by bluebell_ll@Jan 25 2007, 02:06 AM hi, everyone, i met a strange problem.  after i complied the project(standard project, i added user logic and assign pins) in quartus ii 5.0 successfully, and download the .sof file into the altera dev board, stratix edition, when i want to run a simple project in nios ii ide 5.0 with a hello world template, then a problem occurs in ide console.  >>using cable "usb-blaster [usb-0]", device 1, instance 0x00 >>pausing target processor: not responding. >>resetting and trying again: failed >>leaving target processor paused  i search this problem in google and other search engines. fae in altera had explained this problem before, with two possible reasons. one is accidental error between nios ii cpu and ide software through usb-blaster, and you could resolve this problem with downloading the sof file and run again. the other was making the tools consistency(nios ii ide 6.0, quartus ii 6.0), rebuilding the system again.  i followed the instruction, but can not get the right result!  and some guys say it is related with clock and time sequence of sdram, but does not gives the solutions.  3xs for help! <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20845)  --- quote end ---    --- Quote End ---     Hello I had the same problem you had and would like to know what the solution was. Thanks.