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A strange error

Altera_Forum
Honored Contributor II
1,315 Views

Hi ! 

When I exactly follow the 《Nios II Hardware Development Tutorial》 to the end of adding contants ( page 1-23 ) , a strange error say " Error: System.cpu: Nios II debug module requires a clock frequency of at least 20 MHz " . 

But my clock setting is just set to 20 MHz . 

What's the problem ?
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Altera_Forum
Honored Contributor II
401 Views

Try 50 MHz - usually safe

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Altera_Forum
Honored Contributor II
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I set to 20 MHz because my oscillator on development board is 20 MHz . 

Seems I need to use pll to rise the frequency ? 

But the tutorial say "The 

frequency you specify for clk_0 must match the oscillator that drives the FPGA."
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Altera_Forum
Honored Contributor II
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That's an error, it should say it must match the clock signal driving the cpu. 

 

We run the Nios through a PLL all the time. So bumping to 40 , 60, 80, or 100 MHz should be no problem from your 20 MHz source. 

 

Just for grins I would just switch the setting to 20.1 MHz and see if it builds. I never hit that before, but it sounds like someone in the software land should have had made it the limit >= instead of just >. 

 

Pete
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