ABOUT reg.h

[Altera_Forum]

#ifndef __ALTERA_AVALON_LCD_16207_REGS_H__# define __ALTERA_AVALON_LCD_16207_REGS_H__ 

 /* /////////////////////////////////////////////////////////////////////////// // // ALTERA_AVALON_LCD_16207 PERIPHERAL // // Provides a hardware interface that allows software to  // access the two (2) internal 8-bit registers in an Optrex  // model 16207 (or equivalent) character LCD display (the kind // shipped with the Nios Development Kit, 2 rows x 16 columns). // // Because the interface to the LCD module is "not quite Avalon,"  // the hardware in this module ends-up mapping the module&#39;s  // two physical read-write registers into four Avalon-visible // registers: Two read-only registers and two write-only registers. // A picture is worth a thousand words: // // THE REGISTER MAP //  // 7 6 5 4 3 2 1 0 Offset // +-----+-----+-----+-----+-----+-----+-----+-----+ // RS = 0 | Command Register (WRITE-Only) | 0 // +-----+-----+-----+-----+-----+-----+-----+-----+ // RS = 0 | Status Register (READ -Only) | 1 // +-----+-----+-----+-----+-----+-----+-----+-----+ // RS = 1 | Data Register (WRITE-Only) | 2 // +-----+-----+-----+-----+-----+-----+-----+-----+ // RS = 1 | Data Register (READ -Only) | 3 // +-----+-----+-----+-----+-----+-----+-----+-----+ // /////////////////////////////////////////////////////////////////////////// */ # include <io.h> # define IOADDR_ALTERA_AVALON_LCD_16207_COMMAND(base) __IO_CALC_ADDRESS_NATIVE(base, 0)# define IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, data) IOWR(base, 0, data) # define IOADDR_ALTERA_AVALON_LCD_16207_STATUS(base) __IO_CALC_ADDRESS_NATIVE(base, 1)# define IORD_ALTERA_AVALON_LCD_16207_STATUS(base) IORD(base, 1) # define ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK (0x00000080u)# define ALTERA_AVALON_LCD_16207_STATUS_BUSY_OFST (7) # define IOADDR_ALTERA_AVALON_LCD_16207_DATA_WR(base) __IO_CALC_ADDRESS_NATIVE(base, 2)# define IOWR_ALTERA_AVALON_LCD_16207_DATA(base, data) IOWR(base, 2, data) # define IOADDR_ALTERA_AVALON_LCD_16207_DATA_RD(base) __IO_CALC_ADDRESS_NATIVE(base, 3)# define IORD_ALTERA_AVALON_LCD_16207_DATA(base) IORD(base, 3)  # endif    who can tell me why the Command Register Offset is 0,Status Register offset is 1 and the other register offset 1,2

[Altera_Forum]

I don&#39;t really get what you&#39;re asking here. The registers have these offsets because they are at the respective address. And the "other register" offset seems to be 2 and 3, not 1,2?

[Altera_Forum]

thank you! 

my mean is how to set the address offset,Can i set the offset below: IOADDR_ALTERA_AVALON_LCD_16207_COMMAND(base) __IO_CALC_ADDRESS_NATIVE(base, 3) IOADDR_ALTERA_AVALON_LCD_16207_STATUS(base) __IO_CALC_ADDRESS_NATIVE(base, 2) IOADDR_ALTERA_AVALON_LCD_16207_DATA_WR(base) __IO_CALC_ADDRESS_NATIVE(base, 0) IOADDR_ALTERA_AVALON_LCD_16207_DATA_RD(base) __IO_CALC_ADDRESS_NATIVE(base, 1)

[Altera_Forum]

You can only change the base address of the LCD device, you can not change the offsets for the registers inside the device. 

 Are you trying to change the macro for reading/writing the registers? I&#39;m still confused what you are trying to do. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

[Altera_Forum]

thank you , because i want to write a new Peripheral like the component, i don&#39;t write vhdl for the component,so i don&#39;t know how to set the offset.

[Altera_Forum]

Hi, 

  The BADE address of device depend on your definition in SOPC Builder.  And the offset address depend on HDL design files.  So you can&#39;t modify any of them.  FYI. David

[Altera_Forum]

--- Quote Start ---  originally posted by nwpu_zhf2004@Apr 13 2006, 04:38 PM thank you , because i want to write a new peripheral like the component, i don&#39;t write vhdl for the component,so i don&#39;t know how to set the offset. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14331)  --- quote end ---    --- Quote End ---   Hi! Offset of regiters depends on HDL part of component. So, Offset is predefined. You must care with it and any result of changes of offset would be unpredictable.