AGILEX 5 Reset for GTS AXI Streaming IP documentation

[Serge93]

Hello Support,

Where I can find some documentation about the  "Reset for GTS AXI Streaming IP" :

Thank you.
Serge

[SueC_Altera]

Hi Serge,

I did a quick google search and found this: https://www.intel.com/content/www/us/en/docs/programmable/813754/25-1/introduction.html

Let me know if that is what you are looking for

Sue

[Serge93]

Hello Sue,

Thank you for the answer.

I already have this documentation.

Please pay attention to the title : Reset for GTS AXI Streaming IP

You can try to instantiate it in Platform Designer to well identify the IP.

Thanks for help.
Serge

[RongYuan]

Hi Serge,

For Quartus Pro 25.1, you can find Reset signals are described here

6.2.2. Interface Reset Signals

Regards,

Rong

[Serge93]

Hello Rong,

Nice to see you again.

Sorry, but this is the description of the GTS PCIe IP, I am talking about another independant IP, which from what I understand, generates, manages, the Reset Sequence for the GTS PCIe IP.

The 'Reset for GTS AXI Streaming IP' should/can be connected to the GTS PCIe IP.

But I did not find any documentation about the 'Reset for GTS AXI Streaming IP'.

Thanks for help.
Serge

[RongYuan]

This "Reset for GTS AXI Streaming IP" is a support module for user controlling multiple resets easier, you can find a similar one in MCDMA design, however it doesn't have its own user guide. You may refer to 4.3. Implementing Required Resets for some of these reset signals used in MCDMA design.

Regards,

Rong

[Serge93]

Well, the 4.3 section is quite short an do not describe at all the "Reset for GTS AXI Streaming IP" and its ports.

May be later one documentation will appear.

Thanks.
Serge

[RongYuan]

Right. Because these resets belong to different interfaces. For the PCIe part, you may check 2.2. Reset Sequence.

Regards,

Rong