Nios® V/II Embedded Design Suite (EDS)
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Acess data wordwise from Nios II

Honored Contributor II



I have a 16 bit wide Flash memory and a 32 bit wide RAM attached to the Nios II. In the evaluation kit (Altera Embedded Systems Development Kit, Cyclone III Edition) address bit 0 is omitted for the Flash memory and address bits 0 and 1 are omitted for the RAM. 


How can I make sure the data is only addressed wordwise? Or will the Nios II by default address the memory wordwise? 




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Honored Contributor II

If anybody has the same question here is the response I got from the Altera support: 


For masters, the address signal represents a byte address. The value of the address must be aligned to the data width. To write to specific bytes within a data word, the master must use the byteenable signal. For slaves, the inter-connect translates the byte address into a word address in the slave’s address space so that each slave access is for a word of data from the perspective of the slave. For example, address= 0 selects the first word of the slave and address 1 selects the second word of the slave. 


Please refer to the following user guide page 30 "Avalon MM salve addressing".
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