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Arria 10 auto configuration issue with EPCQ-L, Programming file on Nios

Honored Contributor II

Hi Experts, 


Once I posted an article to Altera general discussion, however it would be applicable to Nios forum after some analysis, so I posted here. 


Original inquire URL is here.  



When it generated jic-file, "A.jic" hereinafter, from sof-file, the file caused two symptoms, auto-configuration issue and JTAG port issue. 


1. Although once it was finished program-writing and verification successfully, configuration has not done after power-OFF/ON cycle, i.e. running auto-configuration. Checking ROM via Active Serial port, program was written correctly. And it appeared direct TDI signal on TDO port without any clock shift. 


2. As TDO didn't work after power ON as article 1, it could not write ROM via JTAG. Active Serial port still ran correctly, I could erase ROM, and after that, I could write ROM again via JTAG, but it occurred same symptom as article 1. 


3. I regenerated another jic-file, "B.jic" hereinafter, from same sof-file on QUARTUS-Programmer, then the file was fine, there was no problem. 


4. And even "A.jic" file was fine after writing "B.jic". I have not come across same issue. It appeared three boards I assembled. 


5. "A.jic" was generated by a third party, and then I asked them how to generate "A.jic". They didn't use programmer, use scripted batch-file instead. They followed the documents below for creating the batch file. (

AN736 (


The apparent difference between "A.jic" and "B.jic" was following, checking the jic-files by binary editor. 

After some information header it appeared "FF FF ... FF 6A 6A 6A 6A" on "B.jic". But it appeared another unique code before "6A 6A 6A 6A" on "B.jic".  


I would ask if this script method run correctly even on the current Altera-Intel device. 


I use 10AX016C4U19 and EPCQ-L256. 



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