Arrow Cyclone V SoCKit Hard DDR3 Memory controller interface

Altera_Forum · ‎10-05-2015

Hello all,

I have a query with respect to the implementation of the Hard Memory controller + UniPHY interface for the Cyclone V SoCKIT development board (https://www.arrow.com/en/products/so...nt-tools/#2pne (https://www.arrow.com/en/products/sockit/arrow-development-tools/#2pne))

One of the same reference designs provided with the board shows you the use of the soft memory controller. Does anyone here have experience with the Hard Memory controller?

If so, except for checking the "Enable Hard Memory Interface" and "Enable AFI half clock" are there other settings that need to be changed from the implementation of the soft memory controller?

I am attempting at implementing the same design using hard memory controller. Also, please post if you have a simple reference design that does the same.

Altera_Forum · ‎10-06-2015

Hi David,

I have done exactly what you said and the HMC worked fine in the SoCKit. Also, I left the memory clock frequency at 300MHz even though the Cyclone V's HMC is supposed to handle up to 400MHz.

Try that configuration and use the External Memory Interface Toolkit to confirm it is working properly.

Best regards,

Thiago

Altera_Forum · ‎10-07-2015

Hello Thiago,

Thank you. it works. But, do you have any idea why the design runs only at 300 MHz?

Altera_Forum · ‎10-13-2015

Hello David,

The 300 MHz might be because the soft memory controller is limited to this speed. Did you try increasing it to 400 MHz using the HMC? It will work if the board is not physically limiting it.

Thiago